Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a semiconductor substrate having a device region and a protective region around the device region; a seal ring structure on the semiconductor substrate in the protective region; an electrical interconnect structure on the semiconductor substrate in the device region; an interlayer dielectric layer entirely covering the protective region on the seal ring structure and the electrical interconnect structure; a solder pad electrically connected with the electrical interconnect structure passing through a portion of the interlayer dielectric layer in the device region; a passivation layer on the interlayer dielectric layer and exposing the solder pad; and a conducive wire connected to the solder pad and across over a portion of the passivation layer in the protective region.

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer.

The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.

A testing architecture for integrated circuits on a wafer includes at least one first circuit of a structure TEG realized in a scribe line providing separation between first and second integrated circuits. At least one pad is shared by a second circuit inside at least one of the first and second integrated circuits and the first circuit. Switching circuitry is coupled to the at least one pad and to the first and second circuits.

A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.

A method of forming stacked semiconductor device structure includes providing a first semiconductor device and a second semiconductor device. The first semiconductor device includes a recessed region bounded by sidewall portions and a conductive layer disposed adjoining at least portions of the recessed region. The method includes electrically connecting the second semiconductor device to the conductive layer within the recessed region such that at least a portion of the second semiconductor device is disposed within the recessed region.