This disclosure provides an integrated circuit device that includes a RDL that is interlocked with a bump (or “pillar”). The interlocked interface provides the contact RDL-bump interface with increased structural stability that can better withstand the thermal stresses associated with high performance devices IC devices. The interlock structure mitigates crack/delamination that occurs at the RDL-bump interface in large IC chips that are generally subjected to higher stresses during operation.

A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.

The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad

The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.

A chip includes pads having first connecting surfaces, and conductive structures located on the first connecting surfaces. The conductive structures are disposed on the first connecting surfaces. Each of the conductive structures includes first metal layer, second metal layer, and third metal layer. The first metal layer connects one of the pads, and the second metal layer is disposed between the first metal layer and the third metal layer. On every pad, the first metal layer, the second metal layer, and the third metal layer are stacked along first direction on the first connecting surface of the pad, and the first direction is parallel to normal direction of the first connecting surface, and the first metal layer is made of material comprising gold, and the second metal layer is made of material comprising nickel. A wafer is also provided.

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.

A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.