A semiconductor package includes a semiconductor chip, and including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad of the semiconductor chip and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening, an encapsulant covering at least a portion of the semiconductor chip, and a connection structure disposed on the active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via. The second opening has a width narrower than a width of the first opening.

The present application provides a method for preparing a semiconductor device, include the following steps: forming a source/drain (S/D) region in a semiconductor substrate; forming a bonding pad over the semiconductor substrate; forming a first spacer over a sidewall of the bonding pad; forming a first passivation layer covering the bonding pad and the first spacer; and forming a conductive bump over the first passivation layer, wherein the conductive bump penetrates through the first passivation layer to electrically connect to the bonding pad and the S/D region.

The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

A method includes: providing a semiconductor die having a first main surface, a second main surface opposite the first main surface, and an edge between the first main surface and the second main surface; applying a temporary spacer to a first part of the first main surface of the semiconductor die, the first part being positioned inward from a peripheral part of the first main surface; after applying the temporary spacer, embedding the semiconductor die at least partly in an embedding material, the embedding material covering the edge and the peripheral part of the first main surface of the semiconductor die and contacting a sidewall of the temporary spacer; and after the embedding, removing the temporary spacer from the first main surface of the semiconductor die to expose the first part of the first main surface of the semiconductor die. A semiconductor device produced by the method is also provided.

A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.

A method includes: providing a semiconductor die having a first main surface, a second main surface opposite the first main surface, and an edge between the first main surface and the second main surface; applying a temporary spacer to a first part of the first main surface of the semiconductor die, the first part being positioned inward from a peripheral part of the first main surface; after applying the temporary spacer, embedding the semiconductor die at least partly in an embedding material, the embedding material covering the edge and the peripheral part of the first main surface of the semiconductor die and contacting a sidewall of the temporary spacer; and after the embedding, removing the temporary spacer from the first main surface of the semiconductor die to expose the first part of the first main surface of the semiconductor die. A semiconductor device produced by the method is also provided.

A semiconductor device includes: a first semiconductor die having opposing first and second main surfaces and an edge between the first and second main surfaces; a molding compound covering the edge and a peripheral part of the first main surface of the first semiconductor die, the molding compound including a resin and filler particles embedded within the resin; and a first opening in the molding compound which exposes a first part of the first main surface of the first semiconductor die from the molding compound, the first part being positioned inward from the peripheral part, wherein the first opening in the molding compound has a sidewall, wherein predominantly all of the filler particles disposed along the sidewall of the first opening are fully embedded within the resin and not exposed at all along the sidewall. A semiconductor structure including a semiconductor wafer or panel is also described.

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.