Patent classifications
H01L2224/0221
Semiconductor package
The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed.
WIRE BONDING STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A wire bonding structure and a method of manufacturing the same are provided. The wire bonding structure includes a bonding pad structure, a protection layer and a bonding wire. The bonding pad structure includes a bonding pad and a conductive layer. The bonding pad has an opening. The conductive layer is electrically connected to the bonding pad. At least a portion of the conductive layer is located in the opening of the bonding pad and laterally surrounded by the bonding pad. The protection layer at least covers a portion of a surface of the bonding pad structure. The bonding wire is bonded to the conductive layer of the bonding pad structure.
Semiconductor device
A semiconductor device includes a surface metal formed on a substrate, a first protective film formed on the surface metal, a second protective film having a first portion provided on the first protective film and a second portion continuing to the first portion and provided on the surface metal and being transparent to light, and a metal film having a main body portion provided on the surface metal and a run-on portion continuing to the main body portion and running onto the first protective film, wherein the main body portion is thicker than the first protective film, the first portion is thicker than the run-on portion, and the second portion is thicker than the main body portion.
SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE
A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, and contains nickel or copper, an entire back surface of the bonding layer being electrically connected to and in direct contact with an electrode in the semiconductor device; an anti-oxidation layer disposed on the bonding layer; and a protective layer disposed directly on a top surface of a peripheral portion of the bonding layer on which the anti-oxidation layer is absent, covering an outer peripheral edge of the bonding layer, wherein the protective layer is made of an electrically insulating resin.
DISPLAY APPARATUS
A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group.
SEMICONDUCTOR DEVICE AND POWER AMPLIFIER MODULE
A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
Display apparatus
A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group.
SEMICONDUCTOR PACKAGE
A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.
Semiconductor device and power amplifier module
A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
Semiconductor Package
A semiconductor package includes a semiconductor chip, and including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad of the semiconductor chip and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening, an encapsulant covering at least a portion of the semiconductor chip, and a connection structure disposed on the active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via. The second opening has a width narrower than a width of the first opening.