H01L2224/05023

Dielectric and metallic nanowire bond layers

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

ELECTROLESS NICKEL PLATING SOLUTION
20210371985 · 2021-12-02 ·

An electroless nickel plating solution, including a source of nickel ions, a source of molybdenum ions, a source of tungsten ions, a source of hypophosphite ions at least one complexing agent, at least one organic sulphur containing compound in a concentration of 0.38-38.00 μmol/L, and at least one amino acid in a concentration of 0.67-40.13 mmol/L, and
a method for electroless plating of a nickel alloy layer on a substrate, a nickel alloy layer, and
an article comprising the a nickel alloy layer.

PACKAGE STRUCTURE

A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

IC DEVICE WITH CHIP TO PACKAGE INTERCONNECTS FROM A COPPER METAL INTERCONNECT LEVEL
20210375816 · 2021-12-02 ·

An integrated circuit device (100) and method comprising an IC chip (102) having metal interconnect levels (M1-Mn) including a last copper interconnect level (Mn) and a chip-to-package interconnect (110) overlying and connected to the last copper interconnect level (Mn). The chip-to-package interconnect (110) having a via (112) connected to a first element (306a) of the last copper interconnect level (Mn) and a copper conductive structure (118) (e.g., bump copper). The via (112) includes a barrier material (112a) and a tungsten fill layer (112b), the via coupled between the copper conductive structure (118) and the first element (306a).

FET CONSTRUCTION WITH COPPER PILLARS OR BUMP DIRECTLY OVER THE FET
20220189898 · 2022-06-16 · ·

A method of forming a semiconductor device with a metal pillar overlapping a first top metal interconnect and a second top metal interconnect is disclosed. The metal pillar overlapping the first top metal interconnect and second top metal interconnect is connected to the first top metal interconnect by top metal vias while the second top metal interconnect does not contain top metal vias and remains free of a direct electrical connection to the metal pillar. The metal pillars are attached directly to top metal vias without a bond pad of metal. The elimination of the bond pad layer reduces the mask count, processing, and cost of the device. In addition, the elimination of the bond pad results in reduced die area requirements for the metal pillar.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
20220189895 · 2022-06-16 · ·

A semiconductor device includes a semiconductor substrate configured to include a first electrode layer, and a first barrier layer provided on the first electrode layer and bonded to a metal layer, and a circuit substrate configured to include a second electrode layer, and a second barrier layer provided on the second electrode layer and bonded to the metal layer, wherein the semiconductor substrate including a semiconductor element, and the circuit substrate are bonded via the metal layer containing Sn, a linear expansion coefficient of the first barrier layer is larger than that of the circuit substrate, and a linear expansion coefficient of the second barrier layer is smaller than that of the circuit substrate.

Semiconductor packages and methods of forming same

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

Light emitting apparatus and method for producing the same
11735699 · 2023-08-22 · ·

A light emitting apparatus includes: a mount substrate; at least one light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the at least one light emitting device via at least one adhesive material layer, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the light emitting devices, and wherein a lateral surface of the light transparent member is located laterally inward of a lateral surface of the at least one light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.

TRANSISTOR WITH INTEGRATED PASSIVE COMPONENTS
20230260935 · 2023-08-17 ·

A device includes a semiconductor substrate, a source metallization over an active area of the semiconductor substrate, a through-substrate via electrically connected to the source metallization, and an input bond pad formed in the semiconductor substrate and spaced apart from the active area. The input bond pad is electrically connected to a set of gate structures. The device includes a first inductive coil over the semiconductor substrate between a first portion of the source metallization and a second portion of the source metallization and a first capacitor over the semiconductor substrate between the first portion of the source metallization and the second portion of the source metallization. The first inductive coil and the first capacitor are connected in series between the input bond pad and the through-substrate via.

LIGHT EMITTING APPARATUS AND METHOD FOR PRODUCING THE SAME
20220140212 · 2022-05-05 · ·

A light emitting apparatus includes: a mount substrate; at least one light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the at least one light emitting device via at least one adhesive material layer, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the light emitting devices, and wherein a lateral surface of the light transparent member is located laterally inward of a lateral surface of the at least one light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.