Provided is a semiconductor package structure including a first die having a first bonding structure thereon, a second die having a second bonding structure thereon, a metal circuit structure, and a first protective structure. The second die is bonded to the first die such that a first bonding dielectric layer of the first bonding structure contacts a second bonding dielectric layer of the second bonding structure. The metal circuit structure is disposed over a top surface of the second die. The first protective structure is disposed within the top surface of the second die, and sandwiched between the metal circuit structure and the second die.

A semiconductor device includes: a semiconductor chip having an element forming surface; an insulating layer formed on the element forming surface; a pad wiring layer including a first conductive layer formed on the insulating layer and containing a first conductive material and a second conductive layer formed on the first conductive layer and containing a second conductive material different from the first conductive material, wherein the second conductive layer includes an eaves portion protruding outward with respect to an end surface of the first conductive layer; a bonding member bonded to the pad wiring layer and supplying electric power to an element of the element forming surface; and a coating insulating film selectively formed on the insulating layer below the eaves portion, exposing an upper surface of the insulating layer to a peripheral region of the pad wiring layer, and covering the end surface of the first conductive layer.

The present application discloses a method for fabricating a semiconductor device with liners. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, inwardly forming a trench on the first surface of the substrate, forming a plurality of liners positioned on side surfaces of the trench, forming a first insulating segment filling the trench, and removing part of the substrate from the second surface to expose the first insulating segment and the plurality of liners.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, a conductive structure and at least one via structure. The conductive structure is disposed on an upper surface of the semiconductor substrate. The at least one via structure is disposed in the semiconductor substrate. A portion of the at least one via structure extends beyond the conductive structure.

A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.

A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

A semiconductor device includes front and back side structures on first and second surfaces of a substrate, respectively, and first and second through electrodes penetrating the substrate. The front side structure includes a circuit device, a first front side conductive pattern at a first level, a second front side conductive pattern at a second level, a lower insulating structure, and first to third insulating structures. The back side structure includes a first and a second back side conductive pattern on the same level. The first through electrode contacts the first back side conductive pattern and the first front side conductive pattern. The second through electrode contacts the second back side conductive pattern and the second front side conductive pattern. The first front side conductive pattern penetrates the second insulating structure and at least a portion of the third insulating structure.

Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

An integrated circuit includes a conductive pad. In some embodiments, the conductive pad includes at least one dielectric pattern therein, wherein the at least one dielectric pattern penetrates a surface of the conductive pad. In some embodiments, the conductive pad includes a conductive main body and at least one hole in the conductive main body, wherein the at least one hole penetrates a surface of the conductive main body.