There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

A package structure includes a first thermal dissipation structure, a first semiconductor die, a second semiconductor die. The first thermal dissipation structure includes a semiconductor substrate, conductive vias embedded in the semiconductor substrate, first capacitors electrically connected to the conductive vias, and a thermal transmission structure disposed over the semiconductor substrate and the conductive vias. The first semiconductor die is disposed on the first thermal dissipation structure. The second semiconductor die is disposed on the first semiconductor die opposite to the first thermal dissipation structure.

A display device includes: a circuit substrate including a plurality of pixel circuit units and a plurality of pads on a first surface thereof, the plurality of pads being electrically connected to the pixel circuit units; a display substrate on the circuit substrate and including a plurality of light emitting elements electrically connected to the pixel circuit units; a circuit board on the circuit substrate and including a plurality of circuit board pads electrically connected to the pads; a heat dissipation substrate on a second surface of the circuit substrate, the second surface being opposite to the first surface; and a cover substrate on the heat dissipation substrate and partially overlapping the circuit substrate and the circuit board. Each of the plurality of pads is in direct contact with at least one of the plurality of circuit board pads.

A light-emitting element array includes a semiconductor substrate that is rectangular, a plurality of light-emitting elements on the semiconductor substrate in a row along a first long side of the semiconductor substrate, a plurality of electrode pads on the semiconductor substrate in a plurality of rows along a second long side of the semiconductor substrate, and a plurality of wires on the semiconductor substrate to connect the plurality of light-emitting elements to the plurality of electrode pads. The plurality of electrode pads in the plurality of rows includes a first electrode pad in a row of the plurality of rows closest to the second long side and having a larger area than a second electrode pad in another row of the plurality of rows.

First conductive layer is connected to an impurity region which is a source region or an emitter region. A first conductive layer having an emitter pad and a second conductive layer having a Kelvin emitter pad and a relay pad are separated. A plane occupied area of the Kelvin emitter pad is smaller than a plane occupied area of the emitter pad.

A pixel device including a pixel, a planarization layer covering side surfaces and an upper surface of the pixel, and pixel device pads disposed on the planarization layer, in which the pixel includes a first light emitting stack, a second light emitting stack disposed under the first light emitting stack, a third light emitting stack disposed under the second light emitting stack, and pixel pads electrically connected to the first, second, and through third light emitting stacks, the pixel device pads are electrically connected to the pixel pads through the planarization layer, and at least a portion of each of the pixel device pads extends from an upper region of the pixel to an inner surface of the planarization layer formed between the planarization layer and the pixel.

A sensor package structure is provided and includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a ring-shaped support disposed on the sensor chip, and a light-permeable layer disposed on the ring-shaped support. A top portion of the sensor chip defines a sensing region and a carrying region that surrounds the sensing region and that carries the ring-shaped support. The top portion of the sensor chip includes a passivation layer arranged in the sensing region and the carrying region, a color filter arranged in the sensing region and the carrying region, a pixel layer arranged in the sensing region and formed on the central segment, and a micro-lens layer that is formed on the pixel layer. A part of the color filter layer in the carrying region has a roughened surface and at least partially embedded in the ring-shaped support.

A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.

A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.