An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

A wiring (3) comprising electrical conductors (4, 5, 6, 7) is formed in a dielectric layer (2) on or above a semiconductor substrate (1), an opening is formed in the dielectric layer to uncover a contact pad (8), which is formed by one of the conductors, and a further opening is formed in the dielectric layer to uncover an area of a further conductor (5), separate from the contact pad. The further opening is filled with an electrically conductive material (9), and the dielectric layer is thinned from a side opposite the substrate, so that the electrically conductive material protrudes from the dielectric layer.

A wiring (3) comprising electrical conductors (4, 5, 6, 7) is formed in a dielectric layer (2) on or above a semiconductor substrate (1), an opening is formed in the dielectric layer to uncover a contact pad (8), which is formed by one of the conductors, and a further opening is formed in the dielectric layer to uncover an area of a further conductor (5), separate from the contact pad. The further opening is filled with an electrically conductive material (9), and the dielectric layer is thinned from a side opposite the substrate, so that the electrically conductive material protrudes from the dielectric layer.

A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

An integrated circuit device (100) and method comprising an IC chip (102) having metal interconnect levels (M1-Mn) including a last copper interconnect level (Mn) and a chip-to-package interconnect (110) overlying and connected to the last copper interconnect level (Mn). The chip-to-package interconnect (110) having a via (112) connected to a first element (306a) of the last copper interconnect level (Mn) and a copper conductive structure (118) (e.g., bump copper). The via (112) includes a barrier material (112a) and a tungsten fill layer (112b), the via coupled between the copper conductive structure (118) and the first element (306a).

A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die.

A display device may include: a substrate including a display area having first to third areas, and a non-display area; first pixels in the first area, second pixels in the second area, and third pixels in the third area; a pad part located in the non-display area, and electrically connected to the first to third pixels; a line part including a first line between the pad part and the first area, a second line between the pad part and the second area, and a third line between the pad part and the second area; a bridge line extending in a first direction, and located in the second and third areas; and an extension line extending in a second direction, and located in the second area and electrically connected with the bridge line. The extension line may be electrically connected with the third line.

A display device comprises a first substrate including a first contact hole, a first barrier insulating layer disposed on the first substrate and including second contact holes overlapping the first contact hole, pad electrodes disposed on the first barrier insulating layer, at least a subset of the pad electrodes being disposed in the second contact holes, a display layer disposed on the pad electrodes, and a flexible film disposed below the first substrate and electrically connected to the pad electrodes through the first contact hole and the second contact holes, wherein the first substrate includes a substrate buffer portion overlapping the first contact hole and not-overlapping the second contact holes.