An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.

A semiconductor device includes a semiconductor substrate and a first trench extending into or through the semiconductor substrate from a first side. The first trench is at least partially filled with a conductive material and electrically connected to the semiconductor substrate via a doped semiconductor layer at a sidewall of the first trench. A semiconductor layer adjoins the semiconductor substrate at the first side, and caps the first trench at the first side. A contact is disposed at a second side of the semiconductor substrate opposite to the first side. A method of manufacturing the semiconductor device is also provided.

An integrated circuit (IC) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

A semiconductor memory device including a substrate, first pad layers and a second pad layer on the substrate, a pattern structure including first openings on the first pad layers and a second opening on the second pad layer, and having first and second regions, gate electrodes on the pattern structure and each including a pad region, channel structures penetrating through the gate electrodes in the first region, gate contact plugs electrically connected to the gate electrodes through the pad region of each of the gate electrodes and extending in a vertical direction to penetrate the first openings and connected to the first pad layers, a source contact plug, extending in the vertical direction penetrating the second opening and connected to the second pad layer, and a source connection patter under the pattern structure and in contact with the source contact plug and the second pad layer may be provided.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

A method of manufacturing a semiconductor chip is provided. The method includes: forming a plurality of bonding pads on a semiconductor wafer, sequentially forming an insulating layer and a polishing stop film on the semiconductor wafer to cover the plurality of bonding pads, the insulating layer and the polishing stop film having a plurality of convex portions corresponding to upper portions of the plurality of bonding pads, polishing the plurality of convex portions using the polishing stop film to expose upper surfaces of the plurality of bonding pads, and removing the polishing stop film.

A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.

A semiconductor chip is provided. The semiconductor chip includes: a package substrate; and semiconductor chip stack, wherein the semiconductor chip stack includes a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip includes: a first substrate; a first upper bonding pad; a first upper insulating layer; and a first through electrode, wherein the second semiconductor chip includes: a second substrate; a second wiring structure, wherein the second wiring structure includes a second dielectric layer and a plurality of second wiring layers; a second lower bonding pad; and a second lower insulating layer, wherein the first upper bonding pad and the second lower bonding pad are bonded to each other, and wherein the first upper bonding pad and the second lower bonding pad form an asymmetrical bonding structure, each having an upper-side width is less than a lower-side width.