This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion

Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150 C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150 C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

A substrate includes a base substrate, and a pad at one side of the base substrate, wherein the pad comprises: a first conductive pattern on the base substrate, an insulating layer including a plurality of contact holes exposing a portion of the first conductive pattern, and second conductive patterns separately on the insulating layer and connected to the first conductive pattern through the plurality of contact holes, wherein side surfaces of the second conductive patterns are exposed.

A substrate includes a base substrate, and a pad at one side of the base substrate, wherein the pad comprises: a first conductive pattern on the base substrate, an insulating layer including a plurality of contact holes exposing a portion of the first conductive pattern, and second conductive patterns separately on the insulating layer and connected to the first conductive pattern through the plurality of contact holes, wherein side surfaces of the second conductive patterns are exposed.

A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein.