In a RC-IGBT chip, an anode electrode film and an emitter electrode film are arranged with a distance therebetween. The anode electrode film and the emitter electrode film are electrically connected by a wiring conductor having an external impedance and an external impedance. The external impedance and the external impedance include the resistance of the wiring conductor and the inductance of the wiring conductor.

In a RC-IGBT chip, an anode electrode film and an emitter electrode film are arranged with a distance therebetween. The anode electrode film and the emitter electrode film are electrically connected by a wiring conductor having an external impedance and an external impedance. The external impedance and the external impedance include the resistance of the wiring conductor and the inductance of the wiring conductor.

A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

In one embodiment, a semiconductor device includes a first insulator, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided on the first pad in the second insulator. Furthermore, the first insulator includes a first film that is in contact with the first pad and the second insulator, and a second film provided at an interval from the first pad and the second insulator, and including a portion provided at a same height as at least a portion of the first pad.

In one embodiment, a semiconductor device includes a first insulator, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided on the first pad in the second insulator. Furthermore, the first insulator includes a first film that is in contact with the first pad and the second insulator, and a second film provided at an interval from the first pad and the second insulator, and including a portion provided at a same height as at least a portion of the first pad.

A semiconductor package includes: a base substrate; a semiconductor chip stack including a plurality of semiconductor chips stacked on the base substrate in a first direction and each having an upper surface on which a plurality of pads are disposed; and bonding wire structures electrically connecting the base substrate and the semiconductor chips. The semiconductor chip stack includes a lower semiconductor chip stack and an upper semiconductor chip stack on the lower semiconductor chip stack. The plurality of semiconductor chips include a first semiconductor chip at an uppermost portion of the lower semiconductor chip stack and second semiconductor chips. The plurality of pads include first pads, aligned in a second direction, and second pads, spaced apart from the first pads in a third direction. The first pad on the first semiconductor chip, has an area larger than an area of each of the first pads on the second semiconductor chips.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.

A semiconductor device includes a semiconductor element having a surface on which a first electrode and a second electrode are disposed, a conductor plate having a surface facing the surface of the semiconductor element and electrically connected to the first electrode, an insulating layer disposed on the surface of the conductor plate and covers a part of the surface of the conductor plate, and a conductor circuit pattern disposed on the insulating layer. The conductor circuit pattern has at least one conductor line electrically connected to the semiconductor element. The at least one conductor line includes a conductor line electrically connected to the second electrode.

There is provided a semiconductor device including: a pad portion that is provided above the upper surface of the semiconductor substrate and that is separated from the emitter electrode; a wire wiring portion that is connected to a connection region on an upper surface of the pad portion; a wiring layer that is provided between the semiconductor substrate and the pad portion and that includes a region overlapping the connection region; an interlayer dielectric film that is provided between the wiring layer and the pad portion and that has a through hole below the connection region; a tungsten portion that contains tungsten and that is provided inside the through hole and electrically connects the wiring layer and the pad portion; and a barrier metal layer that contains titanium and that is provided to cover an upper surface of the interlayer dielectric film below the connection region.