In some embodiments, the present disclosure relates to a device that includes an interconnect structure arranged on a frontside of a substrate. The interconnect structure includes interconnect conductive structures embedded within interconnect dielectric layers. A trench extends completely through the substrate to expose multiples ones of the interconnect conductive structures. A bond pad structure is arranged on a backside of the substrate and extends through the trench of the substrate to contact the multiple ones of the interconnect conductive structures. A bonding structure is arranged on the backside of the substrate and electrically contacts the bond pad structure.

A device includes a first laser emitter, a second laser emitter, and a separating portion. The first laser emitter is configured to emit, in an outer circumferential portion of a bonded substrate including a first substrate and a second substrate bonded to each other, a first laser beam into the first substrate from a side of the first substrate to form a modified layer. The second laser emitter is configured to emit a second laser beam to a material layer that is arranged between the first substrate and the second substrate and is provided on the second substrate from a side of the second substrate, to cause peeling between the second substrate and the material layer. The separating portion is configured to separate an outer circumferential portion of the first substrate and an outer circumferential portion of the material layer from the outer circumferential portion of the bonded substrate.

Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.

A semiconductor device having a three-dimensional structure includes a first wafer including a first bonding pad on one surface thereof; a second wafer including a second bonding pad, which is bonded to the first bonding pad, on one surface thereof bonded to the one surface of the first wafer; a plurality of anti-warpage grooves on the one surface of the first wafer, and laid out in a stripe shape; and a plurality of anti-warpage ribs on the one surface of the second wafer and coupled respectively to the plurality of anti-warpage grooves, and laid out in a stripe shape.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device; and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.

A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure. A bonding feature of the second front-side bonding structure includes a first bonding via in contact with the second interconnect structure, a first bonding contact overlying the first bonding via, and a barrier layer interface between a bottom of the first bonding contact and a top of the first bonding via.

A semiconductor device includes a first layer including a plurality of first pads, and a second layer including a plurality of second pads. The plurality of first pads are bonded to the plurality of second pads, respectively. At least one of the first pads or the second pads continuously surrounds an insulating portion.

The present disclosure provides a method for preparing a semiconductor device with a composite dielectric structure. The method includes forming a photoresist pattern structure over a first semiconductor die. The method also includes forming a second dielectric layer surrounding the photoresist pattern structure, and removing the photoresist pattern structure to form a first opening in the second dielectric layer. The method further includes forming dielectric spacers along sidewalls of the first opening, and forming an interconnect structure surrounded by the dielectric spacers. In addition, the method includes bonding a second semiconductor die to the second dielectric layer. The second semiconductor die includes a second conductive pad facing the interconnect structure, and the second conductive pad is electrically connected to the first conductive pad of the first semiconductor die through the interconnect structure.