A display device may include: a substrate including a display area having first to third areas, and a non-display area; first pixels in the first area, second pixels in the second area, and third pixels in the third area; a pad part located in the non-display area, and electrically connected to the first to third pixels; a line part including a first line between the pad part and the first area, a second line between the pad part and the second area, and a third line between the pad part and the second area; a bridge line extending in a first direction, and located in the second and third areas; and an extension line extending in a second direction, and located in the second area and electrically connected with the bridge line. The extension line may be electrically connected with the third line.

A display device comprises a first substrate including a first contact hole, a first barrier insulating layer disposed on the first substrate and including second contact holes overlapping the first contact hole, pad electrodes disposed on the first barrier insulating layer, at least a subset of the pad electrodes being disposed in the second contact holes, a display layer disposed on the pad electrodes, and a flexible film disposed below the first substrate and electrically connected to the pad electrodes through the first contact hole and the second contact holes, wherein the first substrate includes a substrate buffer portion overlapping the first contact hole and not-overlapping the second contact holes.

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness.

A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.

A display apparatus includes: a substrate; a plurality of sub-pixel circuits on the substrate, each of the plurality of sub-pixel circuits including at least one transistor; a plurality of light-emitting diodes electrically connected to the plurality of sub-pixel circuits, respectively, and defining a display area; a pad at a non-display area outside the display area; a conductive line extending toward a first edge of the substrate; and a conductor electrically connecting the conductive line to the pad. The conductor overlaps with the pad, is interposed between a part of the conductive line and a part of the pad, and has an isolated shape in a plan view.

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

A method of treatment of an electronic circuit including at a location at least one electrically-conductive test pad having a first exposed surface. The method includes the at least partial etching of the test pad from the first surface, and the forming on the electronic circuit of an interconnection level covering said location and including, on the side opposite to said location, a second planar surface adapted for the performing of a hybrid molecular bonding.

Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.