A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Structures and methods for reducing thermal expansion mismatch during chip scale packaging are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes a first metal layer over a substrate, a dielectric region, and a polymer region. The first metal layer comprises a first device metal structure. The dielectric region is formed over the first metal layer. The polymer region is formed over the dielectric region. The dielectric region comprises a plurality of metal layers and an inter-metal dielectric layer comprising dielectric material between each pair of two adjacent metal layers in the plurality of metal layers. Each of the plurality of metal layers comprises a dummy metal structure over the first device metal structure. The dummy metal structures in each pair of two adjacent metal layers in the plurality of metal layers shield respectively two non-overlapping portions of the first device metal structure from a top view of the semiconductor structure.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.

Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A semiconductor device according to some example embodiments includes a substrate, an insulating structure covering the substrate, a transistor between the substrate and the insulating structure, a via insulating layer extending through the insulating structure and the substrate, a plurality of via structures extending through the via insulating layer, a plurality of conductive structures respectively connected to the plurality of via structures, and a plurality of bumps respectively connected to the conductive structures.

A packaging structure, a method for manufacturing the same and a semiconductor device are provided. The packaging structure includes a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure, and an insulating layer covering and exposing part of the redistribution layer. The exposed part of the redistribution layer includes at least one first pad. The first pad includes a first area and a second area arranged continuously. The first area is configured for testing. The second area is configured for performing functional interaction corresponding to content of the test.

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

A semiconductor device includes a first redistribution layer pattern, a second redistribution layer pattern, and a recognition mark. The first redistribution layer pattern is formed on a semiconductor substrate. The second redistribution layer pattern, with a bonding pad portion, is disposed on the first redistribution layer pattern. Furthermore, the recognition mark is formed on the first redistribution layer pattern to indicate a position of the bonding pad portion.

A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a plurality of through silicon via (TSV) and a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.