Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

Semiconductor devices may include a die including a semiconductor material. The die may include a first active surface including first integrated circuitry on a first side of the die and a second active surface including second integrated circuitry on a second, opposite side of the die. In some embodiments, the die may include two die portions: a first die portion including the first active surface and a second die portion including the second active surface. The first die portion and the second die portion may be joined together with the first active surface facing away from the second active surface.

A method of protecting optoelectronic devices against electrostatic discharges, each optoelectronic device comprising an optoelectronic circuit comprising at least one optoelectronic component from among a light-emitting diode or a photodiode. The method comprises forming a first wafer, comprising a plurality of copies of the optoelectronic circuit, bonding the first wafer to a support, separating the optoelectronic devices from one another, and removing from the support a plurality of optoelectronic devices from among said optoelectronic devices by means of a gripping system, wherein the gripping system comprises at least one system for protecting optoelectronic devices against electrostatic discharges

Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises connection terminals between a first die and a second die. The first die has signal and peripheral regions and includes first vias on the peripheral region. The second die is on the first die and has second vias on positions that correspond to the first vias. The connection terminals connect the second vias to the first vias. The peripheral region includes first regions adjacent to corners of the first die and second regions adjacent to lateral surfaces of the first die. The connection terminals include first connection terminals on the first regions and second connection terminals on the second regions. A sum of areas of the first connection terminals per unit area on the first regions is greater than that of areas of the second connection terminals per unit area on the second regions.

An integrated circuit device includes: a substrate having an active surface, an inactive surface, a first region and a second region; a device structure on the active surface, and including individual devices disposed in the first region and a target through-region disposed in the second region; a multilayer wiring structure including wiring layers, wherein at least one wiring layer among the wiring layers has a landing pad overlapping the target through-region; and a through-via structure connected to the landing pad by penetrating through the second region and the target through-region, wherein the target through-region includes first insulating material patterns and dummy device patterns, wherein the first insulating material patterns each have a first area, wherein the dummy device patterns are on the active surface and each have a second area smaller than the first area, and wherein the first insulating material patterns are alternatively arranged with the dummy device patterns.

A high-resolution display device is provided. A display device having both high display quality and high resolution is provided. The display device is provided with a structure that inhibits a reduction in contrast due to the light guided by a layer extending across light-emitting elements. A structure body that absorbs or reflects visible light is provided between adjacent light-emitting elements. This structure body absorbs or reflects the light emitted from a light-emitting element and traveling toward an adjacent pixel, whereby a reduction in contrast due to stray light is inhibited.

A semiconductor device includes an insulating structure; a plurality of horizontal layers vertically stacked and spaced apart from each other in the insulating structure; a conductive material pattern contacting the insulating structure; and a vertical structure penetrating through the plurality of horizontal layers and extending into the conductive material pattern in the insulating structure. Each of the plurality of horizontal layers comprises a conductive material, the vertical structure comprises a vertical portion and a protruding portion, the vertical portion of the vertical structure penetrates through the plurality of horizontal layers, the protruding portion of the vertical structure extends from the vertical portion into the conductive material pattern, a width of the vertical portion is greater than a width of the protruding portion, and a side surface of the protruding portion is in contact with the conductive material pattern.

An electronic assembly comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising an integrated circuit contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip bottom surface; and a conductor connecting said integrated circuit contact pad and said component contact pad.

A semiconductor device includes a semiconductor element layer including a semiconductor substrate including a bump area and a dummy bump area. A TSV structure is in the bump area and vertically extends through the semiconductor substrate, a first topmost line is in the bump area and on the TSV structure and electrically connected to the TSV structure, a signal bump is in the bump area and has a first width in a first direction and is electrically connected to the TSV structure via the first topmost line, a second topmost line is in the dummy bump area and has the same vertical level as a vertical level of the first topmost line and extends in the first direction, and a dummy bump is in the dummy bump area and contacts the second topmost line and has a second width in the first direction larger than the first width.

A connector may include: a first substrate having a top surface, a bottom surface opposite to the top surface of the top substrate and a side surface joining an edge of the top surface of the first substrate and joining an edge of the bottom surface of the first substrate; a second substrate having a top surface, a bottom surface opposite to the top surface of the second substrate and a side surface joining an edge of the top surface of the second substrate and joining an edge of the bottom surface of the second substrate, wherein the side surface of the second substrate faces the side surface of the first substrate, wherein the top surfaces of the first and second substrates are coplanar with each other at a top of the connector and the bottom surfaces of the first and second substrates are coplanar with each other at a bottom of the connector; and a plurality of metal traces between, in a first horizontal direction, the side surfaces of the first and second substrates, wherein each of the plurality of metal traces has a top end at the top of the connector and a bottom end at the bottom of the connector.