A light detecting device includes a photoelectric conversion unit configured to generate a photoelectric charge, a first charge holding unit that includes a first capacitive element and holds the photoelectric charge generated by the photoelectric conversion unit, a second charge holding unit configured to hold the photoelectric charge transferred from the first charge holding unit, a first transistor arranged on a wiring connecting the first charge holding unit and the second charge holding unit to transfer the photoelectric charge held in the first charge holding unit to the second charge holding unit, and a second transistor configured to cause a pixel signal of a voltage value corresponding to a charge amount of the photoelectric charge held in the second charge holding unit to appear on a signal line.

A display device includes a driving member which provides an electrical signal and includes a connection terminal which transmits the electrical signal, a pad electrode which receives the electrical signal from the driving member and is electrically connected to the connection terminal of the driving member, an organic layer on the pad electrode, the organic layer including a side surface defining an opening of the organic layer which exposes the pad electrode to outside the organic layer and within the opening, a protrusion protruding from the side surface, and a connection conductive layer which electrically connects the pad electrode to the connection terminal, within the opening of the organic layer, where the connection conductive layer covers each of the pad electrode which is exposed by the opening of the organic layer, the side surface of the organic layer, and the protrusion of the organic layer.

A semiconductor device includes a chip that includes a mounting surface, a non-mounting surface, and a side wall connecting the mounting surface and the non-mounting surface and has an eaves portion protruding further outward than the mounting surface at the side wall and a metal layer that covers the mounting surface.

The present disclosure provides a novel form of a display device which enables semiconductor light emitting elements having a vertical structure to be assembled onto a substrate and then wiring process to be performed stably without any change to the position of the elements during post-processing. The display device according to one embodiment of the present disclosure comprises: a substrate; a pair of assembly electrodes positioned on the substrate; a dielectric layer positioned on the assembly electrodes; a wiring electrode positioned on the dielectric layer and comprising a base electrode part and a low melting point junction; a partition wall which overlaps with a portion of the wiring electrode, is positioned on the dielectric layer, and defines an assembly groove to which a semiconductor light emitting element is assembled; and the vertical semiconductor light emitting element which is assembled in the assembly groove and is electrically connected to the low melting point junction of the wiring electrode, wherein the low melting point junction has a flow stop angle for controlling the thermal flow characteristic of the junction.

An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame.

A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

A direct bond hybridization (DBH) method is provided. The DBH method includes preparing a first underlying layer, a first contact layer disposed on the first underlying layer and a first contact electrically communicative with the first underlying layer and protruding through the first contact layer, preparing a second underlying layer, a second contact electrically communicative with the second underlying layer and formed of softer material than the first contact and a second contact layer disposed on the second underlying layer and defining an aperture about the second contact and a moat at least partially surrounding the second contact and bonding the first and second contact layers whereby the first contact contacts the second contact such that the second contact deforms and expands into the moat.