A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

A display apparatus includes: a circuit substrate; and a pixel array on the circuit substrate and including a plurality of pixels. The pixel array includes: light emitting diode (LED) cells constituting the plurality of pixels, each of the LED cells including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; wavelength converters on the LED cells; an upper semiconductor layer on the LED cells and having a partition structure; a passivation layer on side surfaces of the LED cells; a first electrode along a region of the LED cells to have a grid shape; second electrodes connected to the second conductivity-type semiconductor layers; and reflective layers between the first electrode and the second electrode along the passivation layer on the side surfaces of the LED cells and having surfaces inclined toward outside of the LED cells.

A display device includes a display panel including a display area and a pad area. The display panel includes a base substrate, a pixel, a pad group, an alignment mark, and a protective layer. The pad group includes a plurality of pads arranged in a first direction. The alignment mark is spaced apart from the pad group in the first direction. The protective layer covers the pads and the alignment mark and a plurality of openings respectively exposing upper surfaces of the pads is defined in the protective layer. Each of the pads includes at least one pad pattern, and the alignment mark is disposed in a same layer as a pad pattern spaced farthest from the base substrate among the at least one pad pattern.

In an embodiment a method includes providing the first component part with a partially exposed first insulating layer, a plurality of first through-vias and an exposed first contact layer structured in places and planarized in places, wherein the first through-vias are each laterally enclosed by the first insulating layer, and wherein the first contact layer partially covers the first insulating layer and completely covers the first through-vias; providing the second component part with a partially exposed second insulating layer, a plurality of second through-vias and an exposed second contact layer structured in places and planarized in places, wherein the second through-vias are each laterally enclosed by the second insulating layer, and wherein the second contact layer partially covers the second insulating layer and completely covers the second through-vias and joining the component parts such that the contact layers overlap each other thereby mechanically and electrically connecting the component parts to each other by a direct bonding process at the contact layers.

In an embodiment a method includes providing the first component part with a partially exposed first insulating layer, a plurality of first through-vias and an exposed first contact layer structured in places and planarized in places, wherein the first through-vias are each laterally enclosed by the first insulating layer, and wherein the first contact layer partially covers the first insulating layer and completely covers the first through-vias; providing the second component part with a partially exposed second insulating layer, a plurality of second through-vias and an exposed second contact layer structured in places and planarized in places, wherein the second through-vias are each laterally enclosed by the second insulating layer, and wherein the second contact layer partially covers the second insulating layer and completely covers the second through-vias and joining the component parts such that the contact layers overlap each other thereby mechanically and electrically connecting the component parts to each other by a direct bonding process at the contact layers.

A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.

A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.

A composite integrated circuit (IC) structure includes at least a first IC die in a stack with a second IC die. Each die has a device layer and metallization layers interconnected to transistors of the device layer and terminating at features. First features of the first IC die are primarily of a first composition with a first microstructure. Second features of the second IC die are primarily of a second composition or a second microstructure. A first one of the second features is in direct contact with one of the first features. The second composition has a thermal conductivity at least an order of magnitude lower than that of the first composition and first microstructure. The first composition may have a thermal conductivity at least 40 times that of the second composition or second microstructure.

Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.

Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.