Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

A semiconductor device and a manufacturing method thereof according to the present invention include: a first pad electrode formed in an uppermost wiring layer of a multilayer wiring layer; a first insulating film formed on the first pad electrode; and a first organic insulating film formed over the first insulating film. Also, the semiconductor device and the manufacturing method thereof include: a barrier metal film formed on the first organic insulating film and connected to the first pad electrode; and a conductive film formed on the barrier metal film. Then, a second insulating film made of an inorganic material is formed on an upper surface of the first organic insulating film between the barrier metal film and the first organic insulating film.

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

Provided is a semiconductor integrated circuit device including a plurality of columns of IO cells and having a configuration capable of reducing wiring delays without causing an increase in the area. The semiconductor integrated circuit device includes a first IO cell column group including an IO cell column closest to a periphery of a chip, and a second IO cell column group including an IO cell column adjacent to the first IO cell column group at the side closer to the core region. At least one of the first IO cell column group or the second IO cell column group includes two or more IO cell columns, and the two or more IO cell columns are aligned in the second direction such that the lower power supply voltage regions face each other or the higher power supply voltage regions face each other.

A display device includes a first substrate including a display area, a non-display area, and a plurality of pixel circuit units in the display area and the non-display area, a plurality of light emitting elements on the first substrate in the display area, the plurality of light emitting elements being electrically connected to the pixel circuit units, a hole mask layer on the first substrate and including a plurality of holes corresponding to the light emitting elements, a second substrate on the hole mask layer and including a plurality of open holes corresponding to the plurality of holes, and a plurality of light exit patterns in the plurality of the open holes of the second substrate corresponding to the plurality of holes, wherein each of the light exit patterns includes a first part in one of the plurality of open holes.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.

A display device including a film substrate including first and second surfaces, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface and including an input terminal and a test terminal, which are arranged in a first direction; a first wire extending from the input terminal on the first surface along a second direction, which intersects the first direction; and a second wire including a first extended portion, which extends along the first surface, a second extended portion, which extends along the second surface, and a first via, which penetrates the film substrate and connects the first extended portion and the second extended portion, wherein the first extended portion extends from the test terminal in the second direction and is connected to the first via, and the second extended portion extends from the first via to an edge of the second surface.

Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, an isolator includes a leadframe having first and second die paddles each having opposed first and second surfaces, a first die supported by the first surface of the first die paddle, and a second die supported by the first surface of the second die paddle. The first and second die paddles are configured enhanced creepage characteristics.

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.