A lighting device disclosed in an embodiment of this invention includes a reflective layer, a resin layer disposed on the reflective layer, a substrate disposed on the resin layer and including an electrode layer, a plurality of light emitting devices disposed between the resin layer and the substrate, and a light blocking layer disposed on the substrate, the electrode layer may include a first pattern region disposed adjacent to the light emitting device and a second pattern region disposed outside the first pattern region and having a pattern different in size from the first pattern region, and the light blocking pattern region may overlap in a vertical direction with the first pattern region.

An insulation chip includes a substrate, a first insulator, a first conductor, a second insulator, and a second conductor. The first conductor is embedded in the first insulator and exposed from the first insulator. The second insulator covers the first insulator and the first conductor. The second conductor is disposed on the second insulator. The first conductor, which includes an electrode pad, and the second conductor face each other in a thickness direction perpendicular to the upper surface of the first insulator. The second insulator includes insulating layers arranged on the first insulator and an exposing recess extending through the insulating layers to expose the electrode pad. The wall of the exposing recess is stepped such that the distance to the electrode pad increases from the upper surface of the first insulator toward the upper surface of the second insulator.

A semiconductor device includes: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; second and third semiconductor chips mounted on the second chip mounting portion; and a sealing body for sealing them. Here, the third semiconductor chip includes a first coil and a second coil that are magnetically coupled to each other. Also, the first coil is electrically connected with a first circuit formed in the first semiconductor chip, and the second coil is electrically connected with a second circuit formed in the second semiconductor chip. Also, in cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil. Further, a power consumption during an operation of the second semiconductor chip is greater than a power consumption during an operation of the first semiconductor chip.

An electronic device includes a via-array substrate, an outer layer, and an alignment substrate. The via-array substrate has a plurality of first vias. The outer layer has a plurality of second vias and is disposed on a side of the via-array substrate. The first vias are greater in distribution density or quantity than the second vias. A part of the first vias is electrically connected to the second vias, and another part of the first vias is electrically floating. The alignment substrate includes a core layer disposed on the outer layer, a plurality of conductive traces, a plurality of interconnecting pads, and a plurality of alignment mark pads. The conductive traces are disposed in the core layer. The interconnecting pads and the alignment mark pads are disposed on a surface of the core layer located away from the outer layer. A part of the conductive traces electrically connects a part of the interconnecting pads and a part of the first vias. A pattern of each of the alignment mark pads is different from a pattern of each of the interconnecting pads.