A power module includes a first substrate including a first metal plate, a second substrate spaced apart from the first substrate and having a second metal facing the first substrate, a plurality of power elements that are disposed between the first substrate and the second substrate and include a first electrode and a second electrode. (New) The plurality of power elements include a first power element having the first electrode bonded to the second metal plate, and a second power element having the first electrode bonded to the first metal plate.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.

Provided is an optical semiconductor element in which an unbonded portion between an optical semiconductor chip and a submount is made small, heat dissipation efficiency becomes high, and service life can be made long. The optical semiconductor element can include: a submount; a submount electrode provided on a mounting surface of the submount and having a rectangular shape as a whole; and a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the submount electrode via a bonding layer. The chip electrode has a shape with chipped corners corresponding to four corners of the submount electrode, which has an exposed surface that is a portion exposed from the chip electrode at the four corners and bonded to the chip electrode to coincide with each other. The bonding layer extends to all the four corners of the exposed surface.

A semiconductor device includes: conductive members including first and second members; a first semiconductor element electrically connected to one conductive member; a second semiconductor element electrically connected to one conductive member configured to receive input of a voltage different from that applied to the first semiconductor element; and a sealing resin covering a part of each conductive member, the first semiconductor element, and the second semiconductor element. The voltage applied to the second member differs from the voltage applied to the first member. The sealing resin contains electrically insulating fillers. When a square cross section having a side length equal to of a minimum spacing between two adjacent conductive members is hypothetically defined in the sealing resin, eight or more of the fillers each having a particle size equal to or greater than of the minimum spacing are at least partially contained in the square cross section.

A semiconductor apparatus according to the present invention includes: a semiconductor component including a cell array and a plurality of wirings; and a semiconductor component including a plurality of pads connected to the semiconductor component including the cell array. A first row pad connected to a row wiring connected to a first cell and a second cell, a second row pad connected to a row wiring connected to a third cell and a fourth cell, and a column pad connected to a column wiring connected to the first cell and the third cell are arranged such that a straight line connecting the first row pad and the column pad crosses a straight line connecting the second row pad and the column pad.

A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

The present disclosure relates to a method of hybrid molecular bonding of a first surface of a first electronic circuit to a second surface of a second electronic circuit. The first electronic circuit includes first conductive pads exposed on the first surface and first conductive tracks exposed on the first surface. The length of each first track is equal to at least five times the width of the first track, the first tracks delivering the reference voltage to the first electronic circuit. The second electronic circuit includes second conductive pads exposed on the second surface and second conductive tracks exposed on the second surface. The length of each second track is equal to at least five times the length of the second track. The method comprises placing into contact the first pads with the second pads and the first tracks with the second tracks.

A light emitting diode apparatus includes a substrate, a first conductive type semiconductor layer, a second conductive type semiconductor layer, a mesa, a lower insulating layer, a first pad and a second pad. The substrate has a first surface and a second surface opposite to the first surface. The first conductivity type semiconductor layer is disposed on the first surface of the substrate. The mesa is disposed on the first conductive semiconductor layer and has an active layer and the second conductive semiconductor layer. A peripheral edge of the first conductive semiconductor layer is exposed. The lower insulating layer covers the mesa and the first conductive semiconductor layer and has a plurality of first openings exposing the first conductive semiconductor layer along a peripheral edge of the substrate.

A flip-chip wire bondless power device and method for using a two sided contact bare die power device as a single-connection-level power device. The device uses a top pad solder ball array for connecting a top pad electrically connected to the top contact of the bare die power device and a bottom pad solder ball array for connecting a bottom pad that is electrically through an electrically conductive bottom pad connector that is electrically connected to the bottom contact of the bare die power device using an electrically conductive die-attach material, the top pad and bottom pad, and thereby the top pad solder ball array and the bottom pad solder ball array are planar for flip chip mounting. A trench can be formed between the top pad and bottom pad for isolation and insulation purposes. A method of assembling a flip-chip wire bondless power device is also provided.

An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.