A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

A light emitting diode apparatus includes a substrate, a first conductive type semiconductor layer, a second conductive type semiconductor layer, a mesa, a lower insulating layer, a first pad and a second pad. The substrate has a first surface and a second surface opposite to the first surface. The first conductivity type semiconductor layer is disposed on the first surface of the substrate. The mesa is disposed on the first conductive semiconductor layer and has an active layer and the second conductive semiconductor layer. A peripheral edge of the first conductive semiconductor layer is exposed. The lower insulating layer covers the mesa and the first conductive semiconductor layer and has a plurality of first openings exposing the first conductive semiconductor layer along a peripheral edge of the substrate.

A back-illuminated type MOS (metal-oxide semiconductor) solid-state image pickup device 32 in which micro pads 34, 37 are formed on the wiring layer side and a signal processing chip 33 having micro pads 35, 38 formed on the wiring layer at the positions corresponding to the micro pads 34, 37 of the MOS solid-state image pickup device 32 are connected by micro bumps 36, 39. In a semiconductor module including the MOS type solid-state image pickup device, at the same time an image processing speed can be increased, simultaneity within the picture can be realized and image quality can be improved, a manufacturing process can be facilitated, and a yield can be improved. Also, it becomes possible to decrease a power consumption required when all pixels or a large number of pixels is driven at the same time.

A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

A flip chip IC device utilized in RF transceivers includes a bare die having a number of metalized pads and each metalized pad has a solder ball deposited thereon. The flip chip IC device further includes a substrate having a number of connector pads corresponding to the metalized pads. The connector pads are connected to one or more electronic components disposed on the substrate via a number of connector strips. The bare die is flipped up-side-down such that the metalized solder pads are aligned and connected with the connector pads of the substrate via the solder balls. At least one of the connector strips includes a strip section having an uneven strip width configured to compensate an impedance of a transmission line formed based on a connection between a metalized pad of the bare die and a connector pad of the substrate to match predetermined impedance.

A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

Provided is an optical semiconductor element in which an unbonded portion between an optical semiconductor chip and a submount is made small, heat dissipation efficiency becomes high, and service life can be made long. The optical semiconductor element can include: a submount; a submount electrode provided on a mounting surface of the submount and having a rectangular shape as a whole; and a semiconductor chip including an element substrate, a semiconductor structure layer formed on the element substrate, and a chip electrode bonded to the submount electrode via a bonding layer. The chip electrode has a shape with chipped corners corresponding to four corners of the submount electrode, which has an exposed surface that is a portion exposed from the chip electrode at the four corners and bonded to the chip electrode to coincide with each other. The bonding layer extends to all the four corners of the exposed surface.

The present disclosure provides a method of processing a semiconductor structure. The method includes: placing a first semiconductor structure inside a semiconductor processing apparatus; supplying a solution, wherein the solution is directed toward a surface of the first semiconductor structure, and the solution includes a solvent and a resist; rotating the first semiconductor structure to spread the solution over the surface of the first semiconductor structure; forming a resist layer on the surface of the first semiconductor structure using the resist in the solution; and removing a portion of the solvent from the solution by an exhaust fan disposed adjacent to a periphery of the first semiconductor structure.

A semiconductor package includes a first semiconductor package, a second semiconductor package on the first semiconductor package, and a plurality of connection terminals between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a package substrate, a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package, a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals, and a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals.