A micro-light-emitting diode mounting board includes a substrate having a mount surface receiving multiple micro-LEDs, and at least one pixel unit located on the mount surface and including the multiple micro-LEDs having different emission colors to operate as a basic element of display. The multiple micro-LEDs include vertical stacks of multiple first electrodes, multiple emissive layers, and multiple second electrodes. The at least one pixel unit includes a power electrode pad connected to each of the multiple second electrodes. The power electrode pad is spaced from each of the multiple first electrodes by a distance greater than an interelectrode distance between adjacent first electrodes of the multiple first electrodes.

Implementations of a semiconductor package system may include a first bond wire bonded to a portion of a leadframe and to a pad of a semiconductor die, the first bond wire coupled to one of a power source or a ground; and a second bond wire bonded to the portion of the leadframe and to a control integrated circuit. The portion of the leadframe may form a current sense area and the control integrated circuit may be configured to use the second bond wire and the current sense area to measure a current flowing through the first bond wire during operation.

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, and at least one guard structure including a first guard element, a second guard element, and a third guard element. The first semiconductor substrate and the second semiconductor substrate are bonded to one another at a bonding interface between a surface of the first semiconductor substrate and a surface of the second semiconductor substrate. The first guard element is in the first semiconductor substrate and spaced apart from the third guard element by a portion of the first semiconductor substrate. The second guard element is in the second semiconductor substrate and spaced apart from the third guard element by a portion of the second semiconductor substrate, and the third guard element includes portions in the first surface and the second surface to bond the first semiconductor substrate to the second semiconductor substrate.

Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. An example integrated circuit device includes an integrated circuit, first type bonding pads and second type bonding pads. Each of the first type bonding pads is electrically connected to the integrated circuit and configured to be electrically connected to a corresponding external integrated circuit device. Each of the second type bonding pads is configured to have no electrical connection with the corresponding external integrated circuit device. Each of the first type bonding pads is configured to be electrically connected to a corresponding one of the second type bonding pads. A number of the first type bonding pads can be larger than a number of the second type bonding pads. Each of the second type bonding pads can have a larger pad area for probing than each of the first type bonding pads.

A semiconductor device includes a first lead having a base extending in a first direction, and an IC on the base. The semiconductor device also includes a second lead, a third lead and fourth leads. The second lead includes a first belt-like section on one side of the base in the first direction, extending in a second direction, and paired second belt-like sections extending in the first direction from the first belt-like section. The third lead is on one side in the first direction. The fourth leads are on one side of the third lead in the first direction. First switching elements are bonded to the third lead. Second switching elements are respectively bonded to the fourth leads. The base overlaps with the first belt-like section 121 when viewed in the first direction. At least a part of the base is between the second belt-like sections.

A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

A semiconductor package includes a first substrate having a first surface and including a first electrode, a first bump pad located on the first surface of the first substrate and connected to the first electrode, a second substrate having a second surface facing the first surface of the first substrate and including a second electrode, a second bump pad and neighboring second bump pads on the second surface of the second substrate, and a bump structure. The second bump pad has a recess structure. That is recessed from a side surface of the second bump pad toward a center thereof. The second bump pad may be connected to the second electrode. A bump structure may contact the first bump pad and the second bump pad. The bump structure may have a portion protruding through the recess structure. The neighboring second bump pads may neighbor the second bump pad and include recess structures oriented in different directions.

Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. An example integrated circuit device includes an integrated circuit, first type bonding pads and second type bonding pads. Each of the first type bonding pads is electrically connected to the integrated circuit and configured to be electrically connected to a corresponding external integrated circuit device. Each of the second type bonding pads is configured to have no electrical connection with the corresponding external integrated circuit device. Each of the first type bonding pads is configured to be electrically connected to a corresponding one of the second type bonding pads. A number of the first type bonding pads can be larger than a number of the second type bonding pads. Each of the second type bonding pads can have a larger pad area for probing than each of the first type bonding pads.

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.