A prepreg is used to fabricate a semiconductor package including a chip and a substrate to mount the chip thereon. The prepreg is in a semi-cured state. The substrate includes a cured product of the prepreg. The chip has: a first chip surface located opposite from the substrate; and a second chip surface located opposite from the first chip surface. The prepreg satisfies the relational expression: 0.9≤X.sub.2/X.sub.1≤1.0 (I), where X.sub.1 is a coefficient of thermal expansion of the first chip surface of the chip before the chip is mounted on the substrate, and X.sub.2 is a coefficient of thermal expansion of the first chip surface of the chip after the chip has been mounted on the substrate.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.

An electronic package structure and a chip thereof are provided. The electronic package structure includes a supporting element, a chip, an internal bonding wire, and a plurality of external bonding wires. The supporting element has a chip arrangement portion. The chip has a first surface and a second surface opposite to the first surface. The chip is arranged on the chip arrangement portion with the second surface facing toward the supporting element. The chip includes a first common pad and an individual core pad that are disposed on the first surface. The internal bonding wire is connected between the first common pad and the individual core pad. The external bonding wires are connected between the chip and the supporting element, in which a first external bonding wire of the external bonding wires and the internal bonding wire are jointly connected to the first common pad.

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.