A printed circuit board including an electronic component and a method of producing the same are provided. The printed circuit board includes a multilayered substrate including an insulation layer and an inner circuit layer laminated therein, a cavity disposed in the multilayered substrate, a via disposed in the insulation layer and configured to electrically connect the inner circuit layer with another inner circuit layer, a first electronic component inserted in the cavity, and a bump pad disposed on a surface of the cavity facing the first electronic component, and the bump pad is formed by having the insulation layer and the via exposed to a lateral side of the cavity.

A semiconductor device includes a mounting substrate with a land having a first surface and a second surface higher than the first surface, a side-emission type light emitting device including an external connecting terminal disposed on the first surface, and a bonding member disposed at least on the second surface to bond the external connecting terminal and the land.

The present invention discloses a modularized circuit for isolated circuit, wherein the isolated circuit includes at least two circuit components connecting in parallel and/or series, the circuit components, according to a circuit connection configuration, weld corresponding pins of the components directly, forming an integrated module in accordance with a desired connection method of the circuit, and saving circuit boards and wires; the circuit components are designed as a parallelepiped, and a plurality of bonding pads are arranged on part of an area on a surface of the parallelepiped. Due to constructing a circuit unit by welding connections in a way of building blocks, welding directly between components in a 3D space, comparing to the circuits limited in a circuit board plane as a PCB, it owns a wider design space.

The present application relates to a light emitting diode, a light emitting device, and a display device. The light emitting device includes a light emitting diode and a substrate; the substrate is coated with a bonding substance; the light emitting diode is provided with a positive electrode pad and a negative electrode pad; the surface of the positive electrode pad and/or the negative electrode pad is provided with a plurality of protrusions which are embedded in the bonding substance; and the positive electrode pads and the negative electrode pads are fixed to the substrate through the bonding substance. The embodiment of the present application provides projections on the pad of the light emitting diode, avoids the need of increasing the area of the pad, increases the contact area between the pad and the solder with the constant pad area, improves the bonding stability between the light emitting diode and the substrate, and reduces the production cost.

A semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device. The semiconductor package also includes a lateral bump structure disposed on the side and implementing a lateral signal path of the semiconductor device. The semiconductor package further includes a vertical bump structure disposed over the upper surface and implementing a vertical signal path of the semiconductor device.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

The present invention discloses an implementation method for stacked connection between isolated circuit components, whose setting is according to at least two circuit components connecting in parallel/series in a circuit, wherein, in accordance with a circuit connection configuration, a plurality of corresponding pins of the components are soldered directly, making the components form an integrated module in accordance with a desired connection configuration of the circuit, and saving circuit boards and wires. Comparing to the circuit limited in a PCB in the prior art, it is possible to construct a circuit unit by welding connection in a way of building-block approach, achieving a circuit in a 3D space through directly welding between components, and owning a wider design space, it may shorten the time used for a circuit from design to process.

Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.