A die stack includes: a first die including a first semiconductor substrate; a second die including a second semiconductor substrate; a bonding dielectric structure including a bonding polymer and that bonds the first die and the second die; a bonding interconnect structure that extends through the bonding dielectric structure to bond and electrically connect the first die and the second die; and a bonding dummy pattern that extends through the bonding dielectric structure to bond the first die and the second die. The bonding dummy pattern is electrically conductive and is electrically floated.

A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.

A display device includes a display area; a pad area including a first pad for supplying a data signal to the display area, second pads for transmitting a DC signal, and a dummy pad, wherein each of the first pad, the second pads, and the dummy pad has a surface as a top face thereof, wherein each of the surface of the first pad, the surface of the second pads, and the surface of the dummy pad has a corresponding vertical level in a thickness direction of the display device, wherein the vertical level of the surface of each of the second pads is higher than the vertical level of the surface of the first pad, wherein the vertical level of the surface of the dummy pad is lower than or equal to the vertical level of the surface of the first pad.

A light emitting device including a substrate having a protruding pattern on an upper surface thereof, a first sub-unit disposed on the substrate, a second sub-unit disposed between the substrate and the first sub-unit, a third sub-unit disposed between the substrate and the second sub-unit, a first insulation layer at least partially in contact with side surfaces of the first, second, and third sub-units, and a second insulation layer at least partially overlapping with the first insulation layer, in which at least one of the first insulation layer and the second insulation layer includes a distributed Bragg reflector.

A first semiconductor device includes a first substrate including a first electrode and a second electrode at a first surface side of the first substrate opposite to a light incident surface side of the first substrate; and a second substrate including a photodiode, a transfer transistor, and a third electrode and a fourth electrode at a first surface side of the second substrate facing the first surface of the first substrate, and a plurality of transistors.

A semiconductor device includes a first chip and a second chip bonded to the first chip. The first chip includes: a substrate; a logic circuit disposed on the substrate; and a plurality of first dummy pads that are disposed above the logic circuit, are disposed on a first bonding surface where the first chip is bonded to the second chip, the plurality of first dummy pads not being electrically connected to the logic circuit. The second chip includes a plurality of second dummy pads disposed on the plurality of first dummy pads and a memory cell array provided above the plurality of second dummy pads. A coverage of the first dummy pads on the first bonding surface is different between a first region and a second region, the first region separated from a first end side of the first chip, the second region disposed between the first end side and the first region.

The present disclosure provides a chip structure and a semiconductor structure. The chip structure includes: a substrate; a functional region located on the substrate; a guard ring structure surrounding the functional region; and an auxiliary bonding region located above the guard ring structure, where there is an overlapping region between a projection of at least part of the auxiliary bonding region on the substrate and a projection of the guard ring structure on the substrate.

A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. A seal-ring structure is arranged in a peripheral region of the 3D IC in the first IC die and the second IC die. The seal-ring structure extends from a first semiconductor substrate of the first IC die to a second semiconductor substrate of the second IC die. A plurality of through silicon via (TSV) coupling structures is arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.

A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.