In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Semiconductor devices including one or more interfacing segments patterned within an outer protective layer and associated systems and methods are disclosed herein. The one or more interfacing segments may provide attachment interfaces/surfaces for connection pads. The one or more interfacing segments or a portion thereof may remain uncovered or exposed and provide warpage control for the corresponding semiconductor device.

A semiconductor power device includes a ceramic-metal composite circuit substrate, a flip chip and a metal thermal-conducting layer. The ceramic-metal composite circuit substrate includes first electric-conducting metal pads and a first thermal-conducting metal pad. The first thermal-conducting metal pad is not electrically connected to the first electric-conducting metal pads. The flip chip includes electric-conducting pads and a floating thermal-conducting metal pad. The electric-conducting pads are electrically connected to the first electric-conducting metal pads. The floating thermal-conducting metal pad is not electrically connected to the electric-conducting pads. The metal thermal-conducting layer is disposed on the flip chip.

An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

A semiconductor package includes a first semiconductor chip including a circuit layer on a first substrate, first through silicon vias passing through the first substrate, first lower bump pads on the circuit layer, and a first upper bump pad and a second upper bump pad on a second surface of the first substrate, each of the first upper bump pad and the second upper bump pad connected to a corresponding one of the first through silicon vias. The package includes a second semiconductor chip including a circuit layer on a first surface of a second substrate, and second lower bump pads on the circuit layer on the second substrate. The package includes a first solder bump to bond the first upper bump pad and the second lower bump pad, and a plurality of second solder bumps to bond the second upper bump pad and the second lower bump pads.

An interconnect structure includes a first dielectric layer, a first metal layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer and has a first segment and a second segment separated from the first segment. The metal via includes a first portion between the first and second segments of the first metal layer, and a second portion above the first metal layer. The second metal layer is over the metal via. From a top view, the second metal layer includes a metal line extending across the first and second segments of the first metal layer. From a cross-sectional view, the first portion of the metal via has opposite sidewalls respectively offset from opposite sidewalls of the second portion of the metal via.

A semiconductor package includes: a first semiconductor chip including a first substrate, first through electrodes, first signal bonding pads electrically connected to the first through electrodes, and first dummy bonding pads electrically insulated from the first through electrodes, wherein the first through electrodes penetrate the first substrate; a second semiconductor chip stacked on the first semiconductor chip and including a second substrate and a plurality of second chip pads on the second substrate and respectively corresponding to the first signal bonding pads and the first dummy bonding pads; first conductive bumps between the first signal bonding pads and the corresponding second chip pads; and second conductive bumps between the first dummy bonding pads and the corresponding second chip pads, wherein the first conductive bumps include a signal bump pad and a first solder bump, and the second conductive bumps include a thermal bump pad and a second solder bump.

A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip.