A semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. The semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. The semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.

A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

A hybrid wafer bonding method includes providing a first semiconductor structure and providing a second semiconductor structure. The first semiconductor structure includes a first via structure in a first dielectric layer, the first via structure including a first contact via surface. The second semiconductor structure includes a second via structure in a second dielectric layer, the second via structure including a second contact via surface. The first contact via surface is bonded with the second contact via surface. A barrier structure is formed surrounding the second contact via surface along a lateral direction and extending into each of the first contact via surface and the second dielectric layer in a vertical direction. The first via structure includes first metal impurities doped in a bulk region of the first via structure, and the second via structure includes second metal impurities doped in a bulk region of the second via structure.

A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

Disclosed herein are display systems with multiple display packages. In some examples, a first display package includes a first LED die and a first backplane die. The first LED die includes a wire interface that is symmetric about a first plane. The first backplane die includes input/output (I/O) pads that are electrically connected to the wire interface and symmetric about a second plane, perpendicular to the first plane. A similarly configured second display package includes a second LED die with a wire interface identical in layout to that of the first LED die, and a second backplane die with I/O pads identical in layout to that of the first backplane die. The second LED die can be positioned with respect to the second backplane die as a mirror reflection across the second plane of the position of the first LED die with respect to the first backplane die.

A device includes an array of light sources (e.g., micro-LEDs, micro-RCLEDs, micro-laser: micro-SLEDs, or micro-VCSELs), a dielectric layer on the array of light sources, and a set of metal bonding pads (e.g., copper bonding pads) in the dielectric layer. Each metal bonding pad of the set of metal bonding pads is electrically connected to a respective light source of the array of light sources. Each metal bonding pad of the set of metal bonding pads includes a first portion at a bonding surface and characterized by a first lateral cross-sectional area, and a second portion away from the bonding surface and characterized by a second lateral cross-sectional area larger than two times of the first lateral cross-sectional area. The device can be bonded to a backplane that includes a drive circuit through a low annealing temperature hybrid bonding.

A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

A semiconductor device includes: a resin layer having a resin main surface; a mounting wiring layer arranged on the resin main surface, and having a mounting wiring main surface facing the same side as the resin main surface and a mounting wiring back surface facing the side of the resin main surface; a semiconductor element including an element wiring layer which is mounted on the mounting wiring main surface, has an element wiring main surface facing the side of the resin layer, and is connected to the mounting wiring layer; and a sealing resin which seals the mounting wiring layer and the semiconductor element, wherein the mounting wiring main surface and the element wiring main surface are rough surfaces having a larger surface roughness than the mounting wiring back surface.

Embodiments of the present disclosure are based on using transistors with back-side contacts. Such transistors enable back-side power delivery to IC components (e.g., transistors, etc.) of an IC structure, which may be more advantageous than front-side power delivery in some implementations. Embodiments of the present disclosure are further based on recognition that using a glass support structure at the front side of an IC structure with back-side power delivery may advantageously reduce parasitic effects in the IC structure, e.g., compared to using a silicon-based support structure at the front.