A semiconductor device and methods of forming are provided. The device includes a second die bonded to a first die and a third die bonded to the first die. An isolation material extends along sidewalls of the second die and the third die. A through via extends from the first die into the isolation material. A first passive device disposed in the isolation material, the first passive device being electrically connected to the first die.

Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

A semiconductor device according to the present embodiment includes a substrate having a first semiconductor circuit provided thereon. First pads are located on the substrate. A first insulating layer is located on an outer side of each of the first pads. Second pads are respectively bonded to the first pads. A second insulating layer is located on an outer side of each of the second pads and is bonded to the first insulating layer. The first pads each include a first conductive material, and a first insulating material located on an inner side of the first conductive material on a bonding surface of the first pads and the second pads.

A semiconductor package includes a substrate, an interposer, a primary component layer, a first redistribution layer, multiple solder bumps and a first hybrid bonding structure. The interposer is disposed above the substrate and includes multiple TSV sets. The primary component layer is disposed above the interposer and includes multiple first chips and a first molding material that fills the space between the multiple first chips. The first redistribution layer is disposed between the primary component layer and the interposer and includes at least one portion of an antenna structure. The plurality of solder bumps is disposed between the substrate and the interposer. The first hybrid bonding structure is disposed between the multiple first chips and the multiple TSV sets for electrical connection in between and includes multiple connection components that respectively apply bonding of multiple metal pieces in between.

A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction.

Provided is a semiconductor device, an imaging device, and a manufacturing apparatus, capable of providing a semiconductor substrate maintaining and improving insulating performance. A through hole that penetrates the semiconductor substrate, an electrode at the center of the through hole, and a space around the electrode are included. The through hole also penetrates an insulating film formed on the semiconductor substrate. A barrier metal is further included around the electrode. An insulating film is further included in the semiconductor substrate and the space. The semiconductor device has a multilayer structure, and the electrode connects wirings formed in different layers to each other.

A hybrid wafer bonding method includes providing a first semiconductor structure and providing a second semiconductor structure. The first semiconductor structure includes a first substrate, a first dielectric, and a first via structure. The first via structure includes a first contact via and first metal impurities doped in the first contact via. The second semiconductor structure includes a second substrate, a second dielectric layer, and a second via structure. The second via structure includes a second contact via and second metal impurities doped in the second contact via. The method further includes bonding the first semiconductor structure with the second semiconductor and forming a self-barrier layer by an alloying process. The self-barrier layer is formed by a multi-component oxide corresponding to the first and second metal impurities.

A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer overlapping the first semiconductor layer, and a wiring structure arranged between them. The second semiconductor layer is provided with p-type MIS transistor. A crystal structure of the first semiconductor layer has a first crystal orientation and a second crystal orientation in direction along a principal surface of the first semiconductor layer. A Young's modulus of the first semiconductor layer in a direction along the first crystal orientation is higher than that in a direction along the second crystal orientation. An angle formed by the first crystal orientation and a direction in which a source and a drain of the p-type MIS transistor are arranged is more than 30 degrees and less than 60 degrees, and an angle formed by the second crystal orientation and that direction is 0 degrees or more and 30 degrees or less.

A multi-die apparatus includes a plurality of die groups. Each die group includes a plurality of dies stacked parallel to each other and with an edge surface of each die aligned with a planar side surface. The multi-die apparatus also includes a base substrate structure that has a planar top surface characterized by a given direction of lattice crystalline planes. Each of the plurality of die groups is disposed sideways on the base substrate structure, with the planar side surface of each die group bonded to the planar top surface of the base substrate structure. One or more of the plurality of die groups are arranged in a non-parallel manner relative to the given direction of lattice crystalline planes of the base substrate structure.