A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

A first semiconductor device includes a first substrate including a first electrode and a second electrode at a first surface side of the first substrate opposite to a light incident surface side of the first substrate; and a second substrate including a photodiode, a transfer transistor, and a third electrode and a fourth electrode at a first surface side of the second substrate facing the first surface of the first substrate, and a plurality of transistors.

A bonded assembly includes a first semiconductor die that includes first metallic bonding structures embedded within a first bonding-level dielectric layer, and a second semiconductor die that includes second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding. One of the first metallic bonding structures a pad portion, and a via portion located between the pad portion and the first semiconductor device, the via portion having second tapered sidewalls.

Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

A semiconductor package is provided in which a first insulating layer includes a first recess spaced apart from a first pad in a first direction, and a second insulating layer includes a second recess spaced apart from a second pad in the first direction and overlapping at least a portion of the first recess in a second direction, perpendicular to the first direction, to provide an air gap together with the first recess. The semiconductor package further includes a first bonding surface defined by the first and second insulating layers contacting each other on one side of the air gap, adjacent to the first and second pads, and a second bonding surface defined by the first and second insulating layers contacting each other on another side of the air gap, opposite to the one side.

A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die having a first bonding surface that is formed with a first set of contacts patterned with a first connection pitch. A second semiconductor die has a second bonding surface that is formed with a second set of contacts patterned with a second connection pitch. The second set of contacts are further patterned with a paired offset. The second semiconductor die is bonded to the first semiconductor die such that the first set of contacts is disposed in opposed electrical engagement with at least a portion of the second set of contacts.

A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.