According to one embodiment, a semiconductor device includes a substrate, a first element and a second element on or above a first surface of the substrate, the first element and the second element each including a first terminal, a second terminal, and a gate, a light emitter, a light receiver configured to place the first element and the second element in an ON state or an OFF state according to an emitting state of the light emitter, and a first interconnect electrically coupling the first terminal of the first element and the first terminal of the second element to each other, the first interconnect being a sheet-shaped conductor.

A semiconductor module includes: a stacked substrate; a semiconductor element arranged on an upper surface of the first circuit board; a metal wiring board including a first bonding portion bonded to an upper surface of the semiconductor element with a bonding material; and a sealing resin that seals the stacked substrate, the semiconductor element, and the metal wiring board. The first bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The metal wiring board has a first standing portion standing up from one end of the first bonding portion, and a second standing portion standing up from the other end of the first bonding portion. The first standing portion constitutes a part of a wiring path through which a main current flows. The second standing portion constitutes a non-wiring path through which the main current does not flow.

Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

An electronic device is disclosed which includes: a substrate; a plurality of active elements disposed on the substrate; a common electrode disposed on the active elements and including a plurality of openings; and a plurality of light-emitting elements, at least one of the light-emitting elements disposed on the common electrode partially, wherein the light-emitting elements each include a first pad and a second pad, and the first pad and the second pad are disposed on a same side of each said light-emitting element, wherein the first pad of one of the light-emitting elements is disposed corresponding to one of the openings of the common electrode and the first pad of the one of the light-emitting elements electrically connects to one of the active elements, and the second pad electrically connects to the common electrode.

The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.

A 3D stack includes a first chip having first interconnection pads of rectangular section, the first interconnection pads having a first pitch in a first direction and a second pitch in a second direction perpendicular to the first direction; and a second chip having second interconnection pads, the second interconnection pads having a third pitch in the first direction and a fourth pitch in the second direction, at least one part of the second interconnection pads being in contact with the first interconnection pads to electrically couple the first and second chips. The first interconnection pads have a first dimension in the first direction equal to m times the third pitch and a second dimension in the second direction equal to n times the fourth pitch. The first interconnection pads are separated two by two in the first direction by a first distance equal to q times the third pitch.

A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The first joint pad and the second floating metal are connected to each other, the second floating metal and the first floating metal are connected to each other, and the first floating metal and the second joint pad are connected to each other, whereby the first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.