An embodiment of the disclosed technology provides a semiconductor package including: a substrate; a first chip and a second chip stacked on the substrate, each of the first chip and the second chip including a slice command/address reception pad, a slice command/address transmission pad, a slice data pad, an input buffer connected to the slice command/address reception pad, an output buffer connected to the slice command/address transmission pad and an input/output buffer connected to the slice data pad; a first connection member connecting the slice command/address transmission pad of the first chip to the slice command/address reception pad of the second chip; and a second connection member connecting the slice data pad of the first chip to the slice data pad of the second chip.

Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.

A chip package structure and a storage system are provided. The chip package structure includes a chipset, a first Re-Distribution Layer (RDL), and a bonding pad region. The chipset includes a plurality of chips distributed horizontally. The first RDL is disposed on a first surface of the chipset. The bonding pad region includes a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

Provided is an electronic component capable of reducing a possibility that insulating layers covering from outer edge portions of electrodes to surrounding portions, around the electrodes, of a substrate are separated from the electrodes and the substrate. An electronic component includes: a substrate; an electrode formed on a surface of the substrate; a protective portion covering at least a part of a peripheral portion of the electrode and a surrounding portion, around the electrode, of the surface of the substrate, across outer edge portions of the electrode, and extending in a circumferential direction along the outer edge portions of the electrode; and an extending portion extending, on the surface of the substrate, from the protective portion in an extending direction away from the electrode. A width of the extending portion perpendicular to the extending direction is longer than a width of the protective portion perpendicular to the circumferential direction.

An electronic device includes a multilevel package substrate with first, second, third, and fourth levels, a semiconductor die mounted to the first level, and a conductor backed coplanar waveguide transmission line feed with an interconnect and a conductor, the interconnect including coplanar first, second, and third conductive lines extending in the first level along a first direction from respective ends to an antenna, the second and third conductive lines spaced apart from opposite sides of the first conductive line along an orthogonal second direction, and the conductor extending in the third level under the interconnect and under the antenna.

A method includes forming a first package component, which comprises forming a first dielectric layer having a first top surface, and forming a first conductive feature. The first conductive feature includes a via embedded in the first dielectric layer, and a metal bump having a second top surface higher than the first top surface of the first dielectric layer. The method further includes dispensing a photo-sensitive layer, with the photo-sensitive layer covering the metal bump, and performing a photolithography process to form a recess in the photo-sensitive layer. The metal bump is exposed to the recess, and the photo-sensitive layer has a third top surface higher than the metal bump. A second package component is bonded to the first package component, and a solder region extends into the recess to bond the metal bump to a second conductive feature in the second package component.

The semiconductor device may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. Each lower pad may be provided such that a width of a top surface thereof is smaller than a width of a bottom surface thereof. The lower pads may include first, second, and third lower pads. In a plan view, the first and third lower pads may be adjacent to center and edge portions of the substrate, respectively, and the second lower pad may be disposed therebetween. A width of a bottom surface of the second lower pad may be smaller than that of the first lower pad and may be larger than that of the third lower pad.