A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

A semiconductor package includes: a first semiconductor chip; a second semiconductor chip; and a bonding structure at an interface between the first and second semiconductor chips. The bonding structure includes: a first bonding insulating layer on the first semiconductor chip; a first connection pad in a first pad opening formed in the first bonding insulating layer, the first connection pad including a first pad layer, a first interface layer including a copper oxide, and a first capping layer; a second bonding insulating layer on the second semiconductor chip; and a second connection pad in a second pad opening formed in the second bonding insulating layer, the second connection pad including a second pad layer, a second interface layer including a copper oxide, and a second capping layer. The first and second capping layers include copper monocrystal layers having a (111) orientation.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.

Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.

A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a plurality of channel structures each extending vertically through the memory stack, a conductive layer in contact with source ends of the plurality of channel structures, a first source contact electrically connected to the channel structures, and a second source contact electrically connected to the channel structures.

In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.