A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A semiconductor device including a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure and a second connector structure is provided. The first conductive pad is disposed on the semiconductor die, wherein the first conductive pad has a first lateral dimension. The second conductive pad is disposed on the semiconductor die, wherein the second conductive pad has a second lateral dimension. The first connector structure is disposed on the first conductive pad, wherein the first connector structure has a third lateral dimension greater than the first lateral dimension. The second connector structure is disposed on the second conductive pad, wherein the second connector structure has a fourth lateral dimension smaller than the second lateral dimension.

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in direct contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion. The first portion is between the neck portion and the conductive pad. The neck portion is narrower than the first portion and narrower than the second portion.

A display device may include: a substrate including a display area and a non-display area; and a pixel located in the display area, the pixel having an emission area and a pixel circuit area. The pixel may include: at least one transistor located in the pixel circuit area; a first pad electrode and a second pad electrode spaced from each other and located in the emission area, the first pad electrode and the second pad electrode being electrically connected to the at least one transistor; a first through hole penetrating one region of the first pad electrode; a second through hole penetrating one region of the second pad electrode; and a light emitting element located in the emission area, the light emitting element being electrically connected to the first pad electrode and the second pad electrode.

A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

The present application discloses a semiconductor device with a barrier layer including aluminum fluoride and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a circuit layer positioned on the substrate, a pad layer positioned in the circuit layer and including aluminum and copper, a first barrier layer positioned on the pad layer and including aluminum fluoride, and a first connector positioned on the first barrier layer.

A method of manufacturing a semiconductor device includes following operations. A substrate is received. An electrical conductor is formed over a surface of the substrate. A photo-curable material is selectively dispensed over the surface of the substrate. The photo-curable material is irradiated to form a passivation layer is formed over the surface of the substrate. The passivation layer partially covers an edge of the electrical conductor.

According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

Provided is a semiconductor package including a first bump pad on a first substrate, a second bump pad on a second substrate, a core material for reverse reflow between the first bump pad and the second bump pad, and a solder member forming a solder layer on the core material for reverse reflow. The solder member is in contact with the first bump pad and the second bump pad. Each of a first diameter of the first bump pad and a second diameter of the second bump pad is at least about 1.1 times greater than a third diameter of the core material for reverse reflow. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.