This present application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method includes: forming an encapsulating structure, the encapsulating structure including an encapsulation layer and a chip, the chip provided on a front side thereof with a plurality of bonding pads, the encapsulation layer covering at least side faces of the chip; forming a rewiring layer on the side of the encapsulating structure close to the front side of the chip, the rewiring layer configured for external connection of the bonding pads on the chip; forming a dielectric layer, the dielectric layer covering the rewiring layer, the dielectric layer provided therein with a through hole in which the rewiring layer is exposed; and forming a pin layer on the side of the dielectric layer away from the chip, the pin layer electrically connected to the rewiring layer through the through hole.

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.

A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.

A semiconductor device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer. The conductive pad is between the interconnect layer and the conductive seed layer.

Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.

A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections.

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.