Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.

Object is to provide an etching solution which generates less foam and can etch copper or copper alloy at high selectivity when used in a step of etching copper or 5 copper alloy in an electronic substrate having both of copper or copper alloy and nickel. The etching solution to be used in a step of selectively etching copper or copper alloy in an electronic substrate having both of copper or copper alloy and nickel has, as essential components thereof, (A) a linear alkanolamine, (B) a chelating agent having an acid group in the molecule thereof, and (C) hydrogen peroxide.

A semiconductor device with a ring structure surrounding a through silicon via (TSV) electrode and a method for forming the same are disclosed. The method includes receiving a substrate including a back side and a front side having a conductor thereon, forming a via hole in the substrate and exposing the conductor, forming a groove extending from the back side into the substrate and surrounding the via hole, forming a first material layer in the via hole, and forming a second material layer in the groove. The groove filled with the second material layer forms the ring structure, while the via hole filled with the first material layer forms the TSV electrode.

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

According to an embodiment, a method of manufacturing a semiconductor device includes forming a first opening that extends from a second surface of a semiconductor substrate opposite to a first surface toward the first surface and extending to a first insulating layer in the semiconductor substrate, performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening, forming a second insulating layer on a side wall of the semiconductor substrate in the first opening, performing a second annealing process after formation of the second insulating layer, forming a second opening that extends to the conductive layer in the first insulating layer through the first opening, and forming a via that is connected to the conductive layer in the first and second openings.

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

A method includes forming a semiconductor device comprising a semiconductor die surrounded by a molding material, wherein a contact metal of the semiconductor device has an exposed edge, placing the semiconductor device into a tray having an inner wall and an outer wall, wherein the inner wall is underneath the semiconductor device and between an outer edge of the semiconductor device and an outer edge of bumps of the semiconductor device, depositing a metal shielding layer on the semiconductor device and the tray, wherein the metal shielding layer is in direct contact with the exposed edge of the contact metal and separating the semiconductor device from the tray.

In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer.

This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip. The plurality of semiconductor chips are stacked such that the bump electrodes provided thereon are electrically connected in the order of stacking of the semiconductor chips, while the side faces on which the identification sections are formed are oriented in the same direction.