Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded by an insulating adhesive.

An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided.

A semiconductor device includes a chip having a main surface, a main surface electrode arranged on the main surface, and a terminal electrode that has a conductor layer covering the main surface electrode and a gap portion penetrating the conductor layer in a thickness direction as viewed in cross section, and that is fixed to a same potential as that of the main surface electrode.

Performance of an electronic apparatus is improved. A display apparatus includes: a substrate; a wiring arranged on the substrate; an insulating layer being an inorganic insulating layer made of an inorganic material and covering the wiring; and a bump electrode being connected to the wiring and protruding from the insulating layer. The bump electrode includes: a first conductor portion being made of a first metal material and being connected to the wiring; and a second conductor portion being made of solder containing tin and being arranged on the first conductor portion. The first conductor portion includes: a first portion being connected to the wiring at a position overlapping a first opening formed in the insulating layer; and a second portion separating from the first portion and being connected to the wiring at a position overlapping a second opening formed in the insulating layer.

An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.

A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.

A composite bump includes a plurality of first bumps that is metal-bonded to an electrode pad of a semiconductor chip, and a second bump that is metal-bonded to the plurality of first bumps.

A method for forming a composite bump, includes forming a plurality of first bumps to be metal-bonded to an electrode pad of a semiconductor chip, and forming a second bump to be metal-bonded to the plurality of first bumps.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a passivation film covering the surface insulating-film and surface electrode on the surface insulating-film, establishing a groove that exposes a central part of the surface electrode, a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film, and micro-bumps arranged on the barrier-metal film located on the passivation film.

A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a passivation film covering the surface insulating-film and surface electrode on the surface insulating-film, establishing a groove that exposes a central part of the surface electrode, a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film, and micro-bumps arranged on the barrier-metal film located on the passivation film.