A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

An antenna module includes an antenna substrate, a first semiconductor package, disposed on the antenna substrate, including a first connection member including one or more first redistribution layers, electrically connected to the antenna substrate, and a first semiconductor chip disposed on the first connection member, and a second semiconductor package, disposed on the antenna substrate to be spaced apart from the first semiconductor package, including a second connection member including one or more second redistribution layers, electrically connected to the antenna substrate, and a second semiconductor chip disposed on the second connection member. The first semiconductor chip and the second semiconductor chip are different types of semiconductor chips.

An antenna module includes an antenna substrate, a first semiconductor package, disposed on the antenna substrate, including a first connection member including one or more first redistribution layers, electrically connected to the antenna substrate, and a first semiconductor chip disposed on the first connection member, and a second semiconductor package, disposed on the antenna substrate to be spaced apart from the first semiconductor package, including a second connection member including one or more second redistribution layers, electrically connected to the antenna substrate, and a second semiconductor chip disposed on the second connection member. The first semiconductor chip and the second semiconductor chip are different types of semiconductor chips.

An integrated circuit package that includes a liquid phase thermal interface material (TIM) is described. The package may include any number of die. The liquid phase TIM can be sealed in a chamber between a die and an integrated heat spreader and bounded on the sides by a perimeter layer. The liquid phase TIM can be fixed in place or circulated, depending on application. A thermal conductivity of the liquid phase TIM can be at least 15 Watts/meter-Kelvin, according to some embodiments. A liquid phase TIM eliminates failure mechanisms present in solid phase TIMs, such as cracking due to warpage and uncontained flow out of the module.

An integrated circuit package that includes a liquid phase thermal interface material (TIM) is described. The package may include any number of die. The liquid phase TIM can be sealed in a chamber between a die and an integrated heat spreader and bounded on the sides by a perimeter layer. The liquid phase TIM can be fixed in place or circulated, depending on application. A thermal conductivity of the liquid phase TIM can be at least 15 Watts/meter-Kelvin, according to some embodiments. A liquid phase TIM eliminates failure mechanisms present in solid phase TIMs, such as cracking due to warpage and uncontained flow out of the module.