A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A manufacturing method of an electronic apparatus is provided, and the manufacturing method includes following steps. A substrate is provided. A plurality of first bonding pads are formed on the substrate. A plurality of electronic devices are provided, and each of the electronic devices includes at least one second bonding pad. The second bonding pads of the electronic devices corresponding to the first bonding pads are laminated onto the corresponding first bonding pads on the substrate, so as to bond the electronic devices to the substrate. The corresponding first and second bonding pads respectively have bonding surfaces with different surface topographies. The manufacturing method of the electronic apparatus is capable of reducing short circuit during a bonding process or improving a bonding yield.

A manufacturing method of an electronic apparatus is provided, and the manufacturing method includes following steps. A substrate is provided. A plurality of first bonding pads are formed on the substrate. A plurality of electronic devices are provided, and each of the electronic devices includes at least one second bonding pad. The second bonding pads of the electronic devices corresponding to the first bonding pads are laminated onto the corresponding first bonding pads on the substrate, so as to bond the electronic devices to the substrate. The corresponding first and second bonding pads respectively have bonding surfaces with different surface topographies. The manufacturing method of the electronic apparatus is capable of reducing short circuit during a bonding process or improving a bonding yield.

The semiconductor device includes: a semiconductor substrate; a conductor layer formed over the semiconductor substrate and having an upper surface and a lower surface; a conductive pillar formed on the upper surface of the conductor layer and having an upper surface, a lower surface, and a sidewall; a protection film covering the upper surface of the conductor layer and having an opening which exposes the upper surface and the sidewall of the conductive pillar; and a protection film covering the sidewall of the conductive pillar. Then, in plan view, the opening of the protection film is wider than the upper surface of the conductive pillar and exposes an entire region of an upper surface of the conductive pillar.

The semiconductor device includes: a semiconductor substrate; a conductor layer formed over the semiconductor substrate and having an upper surface and a lower surface; a conductive pillar formed on the upper surface of the conductor layer and having an upper surface, a lower surface, and a sidewall; a protection film covering the upper surface of the conductor layer and having an opening which exposes the upper surface and the sidewall of the conductive pillar; and a protection film covering the sidewall of the conductive pillar. Then, in plan view, the opening of the protection film is wider than the upper surface of the conductive pillar and exposes an entire region of an upper surface of the conductive pillar.

Provided is a multilayer substrate including laminated semiconductor substrates each having a penetrating hole (hereinafter referred to as through hole) having a plated film formed in the inner surface. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are selectively present at a position where the through holes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through holes are connected by the conductive particles, and the semiconductor substrates each having the through hole are bonded by an insulating adhesive.

Provided is a multilayer substrate including laminated semiconductor substrates each having a penetrating hole (hereinafter referred to as through hole) having a plated film formed in the inner surface. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are selectively present at a position where the through holes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through holes are connected by the conductive particles, and the semiconductor substrates each having the through hole are bonded by an insulating adhesive.

An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.