This application discloses a chip power supply system, a chip, a PCB, and a computer device. The chip power supply system includes a first printed circuit board (PCB), a chip, a power controller, and an inductor module. The first PCB includes N vias, first ends of the N vias are located at a top layer of the PCB, and second ends of the N vias are located at a bottom layer of the first PCB. The chip is coupled to the top layer of the first PCB through N power supply contacts and the first ends of the N vias. The inductor module is coupled to the chip through M power supply contacts and the second ends of M vias of the N vias. The power controller is coupled to the inductor module through the first PCB, and the power controller is configured to control the inductor module to supply power to the chip.

An electronic device includes an electronic chip located between a cover and an interconnection substrate. The electronic chip has contact pads located in front of a first surface of the interconnection substrate. At least one metal region (for example extending on the front surface) thermally couples at least one contact pad of the electronic chip to the cover.

Electrical devices, semiconductor packages and methods of forming the same are provided. One of the electrical devices includes a substrate, a conductive pad, a conductive pillar and a solder region. The substrate has a surface. The conductive pad is disposed on the surface of the substrate. The conductive pillar is disposed on and electrically connected to the conductive pad, wherein a top surface of the conductive pillar is inclined with respect to the surface of the substrate. The solder region is disposed on the top surface of the conductive pillar.

A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.

A semiconductor device includes at least one transistor disposed on or in a substrate. The transistor is a bipolar transistor including an emitter, a base, and a collector, or a field-effect transistor including a source, a gate, and a drain. At least one first bump connected to the emitter or the source is disposed on the substrate. Furthermore, at least three second bumps connected to the collector or the drain are disposed on the substrate. In plan view, a geometric center of the at least one first bump is located inside a polygon whose vertices correspond to geometric centers of the at least three second bumps.

A semiconductor device includes at least one transistor disposed on or in a substrate. The transistor is a bipolar transistor including an emitter, a base, and a collector, or a field-effect transistor including a source, a gate, and a drain. At least one first bump connected to the emitter or the source is disposed on the substrate. Furthermore, at least three second bumps connected to the collector or the drain are disposed on the substrate. In plan view, a geometric center of the at least one first bump is located inside a polygon whose vertices correspond to geometric centers of the at least three second bumps.

A semiconductor device is disclosed including semiconductor dies stacked with an offset in two orthogonal directions. TSVs may then be formed connecting corresponding die bond pads on respective dies in the stack. By offsetting the dies in two orthogonal directions, the overall stepped offset, and consequently the size of the unused keep-out area of the stack, is reduced.

A semiconductor package includes a semiconductor chip that includes a first region and a second region spaced apart from the first region; a plurality of connection bumps disposed under the first region of the semiconductor chip; and a protection layer that covers a bottom surface of the semiconductor chip in the second region, wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps. The semiconductor chip of the semiconductor package is protected by the protection layer.

A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides.

A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.