Disclosed is a fan-out wafer level packaging (FOWLP) apparatus includes a semiconductor die having at least one input/output (I/O) connection, a first plurality of package balls having a first package ball layout, a first conductive layer forming a first redistribution layer (RDL) and configured to electrically couple to the first plurality of package balls, and a second conductive layer forming a second RDL and including at least one conductive pillar configured to electrically couple the at least one I/O connection of the semiconductor die to the first conductive layer, wherein the second conductive layer enables the semiconductor die to be electrically coupled to a second plurality of package balls having a second package ball layout without a change in position of the at least one I/O connection of the semiconductor die.

A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump.

A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less.

A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less.

A flip-chip die package includes a substrate, a die, a plurality of conductive bumps, and a first metal structure, where an upper surface of the die is electrically coupled, using the conductive bumps, to a surface that is of the substrate and that faces the die, and the first metal structure includes a plurality of first metal rods disposed between the substrate and the die, where each first metal rod is electrically coupled to the substrate and the die, and the first metal rods are arranged around a first active functional circuit, and the first active functional circuit includes an electromagnetic radiation capability or an electromagnetic receiving capability in the die.

A semiconductor package includes a semiconductor chip with a normal connection electrode and a measurement connection electrode, formed on a first surface, and a substrate with a normal substrate pad, connected to the normal connection electrode, and a measurement substrate pad, connected to the measurement connection electrode. The normal substrate pad and the measurement substrate pad are formed on a surface that faces the first surface. The measurement connection electrode includes first and second edge measurement connection electrodes and first and second center measurement connection electrodes. The measurement substrate pad includes a center measurement substrate pad, a first edge measurement substrate pad, and a second edge measurement substrate pad. The first edge measurement connection electrode and the first center measurement connection electrode are electrically connected to each other, and the second edge measurement connection electrode and the second center measurement connection electrode are electrically connected to each other.

A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.

A technique capable of improving a performance of a semiconductor detector is provided. The semiconductor detector is made based on injection of an underfill into a gap between a first semiconductor chip and a second semiconductor chip in a flip-chip connection state, but the underfill is not formed in periphery of a connection structure connecting a reading electrode pad and a gate terminal through a bump electrode.

An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.

An electronic device has a plurality of integrated circuits fixed to a support between transmitting and receiving antennas. An integrated circuit generates a synchronization signal supplied to the other integrated circuits. Each integrated circuit is formed in a die integrating electronic components and overlaid by a connection region according to the Flip-Chip Ball-Grid-array or embedded Wafer Level BGA. A plurality of solder balls for each integrated circuit is electrically coupled to the electronic components and bonded between the respective integrated circuit and the support. The solder balls are arranged in an array, aligned along a plurality of lines parallel to a direction, wherein the plurality of lines comprises an empty line along which no solder balls are present. A conductive synchronization path is formed on the support and extends along the empty line of at least one integrated circuit, between the solder balls of the latter.