A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate.

Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

A semiconductor package includes a redistribution layer (RDL) structure, a first die, a molding compound and an interconnect structure. The first die is disposed on the RDL structure. The molding compound is disposed on the RDL structure. The interconnect structure electrically connects the first die to the RDL structure.

A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate.

Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

An electronic component includes a die, a first protective layer, a second protective layer, a first conductive pillar and a second conductive pillar. The die includes a conductive pad. The first protective layer is disposed on the die. The first protective layer defines a first opening to expose the conductive pad of the die. The second protective layer is disposed on the first protective layer. The second protective layer defines a second opening and a first recess. The second opening exposes the conductive pad of the die. The first conductive pillar is disposed within the second opening and electrically connected to the conductive pad. The second conductive pillar is disposed within the first recess. A height of the first conductive pillar is substantially equal to a height of the second conductive pillar. A bottom surface of the first recess is disposed between a top surface of the first protective layer and a top surface of the second protective layer.

Wafer-level (chip-scale) package semiconductor devices are described that have bump assemblies configured to maintain standoff (bump) height. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., do not include a core). The array further includes at least one second bump assembly including a solder bump having a core configured to maintain standoff height of the wafer-level package device.

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided.

Disclosed are a drive integrated circuit (IC) capable of being applied to all of a chip on film (COF) type and a chip on glass (COG) type and a display device including the drive IC. The drive IC includes an input pad part including a plurality of input bumps and an output pad part including a plurality of first diode parts, a plurality of second diode parts, and a plurality of output bumps. At least two of the plurality of output bumps overlap the plurality of first diode parts and the plurality of second diode parts, and a first output bump of the at least two output bumps is connected to at least one of the plurality of first diode parts and at least one of the plurality of second diode parts.