An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

A semiconductor system includes a semiconductor chip comprising a RF circuit, a buffer layer over the RF circuit and a plurality of bumps over the buffer layer, wherein the plurality of bumps comprising at least one functional bump electrically connected to the RF circuit, and at least one dummy bump which is maintained at a distance from the RF circuit and prevented from being electrically connected to the RF circuit by the buffer layer, a conductive layer disposed over the semiconductor chip and coupled to the plurality of bumps through a plurality of vias, a feedline structure disposed over the conductive layer, wherein the feedline structure is electrically coupled to the RF circuit, and a plurality of antennas disposed over the feedline structure, wherein at least one antenna of the plurality of antennas is coupled to the RF circuit through the feedline structure.

An IC package, an electronic assembly, and methods of preventing warpage of components of an electronic assembly during fabrication of the electronic assembly are shown. An IC package including an adhesive disposed at or near at least one of four corners of a die of the IC package is shown. An electronic assembly including an IC package that includes an adhesive disposed at or near at least one of four corners of a second surface of a first substrate is shown. Methods of preventing warpage of components of an electronic assembly during fabrication of the electronic assembly that include applying an adhesive to at least one of four corners of a first surface of a first component are shown.

The disclosure relates to a semiconductor structure, including: a substrate, a bonding pad, a first protective layer, a redistribution layer, a connecting plug, bumps, and a second protective layer. The redistribution layer includes a first metal line and a second metal line. Since the second metal line and the first metal line are of the same height, so the bumps on the first metal line and the second metal line are equivalently formed on the same layer. The coplanarity of the bumps on the metal lines is relatively high. The second metal line does not make any electrical connection to the pad so the bumps formed on the second metal line do not play a conductive role. When the substrate warps, the stress is transferred to the first protective layer. Thus, bumps in the substrate made according to the present application are coplanar, which reduces the probability of poor wetting when flip-chip package on the substrate, and improves the reliability of the entire package.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, and a redistribution structure disposed on the first semiconductor die and the insulating encapsulation. The first semiconductor die includes a first contact region and a first non-contact region in proximity to the first contact region. The first semiconductor die includes a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, and the first electrical connector is electrically connected to a first integrated circuit (IC) component in the first semiconductor die. The first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure.

An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

[Object] To provide an electronic device, a part mounting board, and an electronic apparatus that are capable of preventing warpage of a board from occurring. [Solving Means] An electronic device according to an embodiment of the present technology includes a first circuit board and a second circuit board. The first circuit board includes a first main surface, a second main surface, and a plurality of external terminals. The plurality of external terminals include a first terminal group located at an outermost periphery of the first main surface, and are arranged on the first main surface in a matrix pattern. The second circuit board includes a terminal surface facing the second main surface, and a plurality of connection terminals. The plurality of connection terminals include a second terminal group that is arranged on the terminal surface and faces at least a part of the first terminal group, and are electrically connected to the second main surface.

A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.

A method of fabricating a semiconductor device is provided, including providing a base substrate and a die stacking unit mounted on the base substrate. Conductive joints are connected between two adjacent dies of the die stacking unit. The method further includes providing dummy micro bumps and dummy pads between the two adjacent dies and between the conductive joints. The dummy micro bumps and the dummy pads are connected to one of the two adjacent dies but not to the other, and the dummy micro bumps are formed on some of the dummy pads but not on all of the dummy pads. In addition, the method includes filling the gaps between the base substrate, all dies of the die stacking unit, the conductive joints, the dummy micro bumps, and the dummy pads with an underfill material by capillary attraction.