H01L2224/16054

SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE
20240421112 · 2024-12-19 · ·

A semiconductor element includes: an element front surface and an element back surface facing an opposite side from the element front surface; first and second electrodes that are formed over the element front surface; first electrode terminals in contact with the first electrode; second electrode terminals in contact with the second electrode; a first region in which the first electrode terminals are arranged; and a second region in which the second electrode terminals are arranged, wherein the number of the second electrode terminals per unit area in the second region is smaller than the number of the first electrode terminals per unit area in the first region, and wherein an area of each of the second electrode terminals is larger than an area of each of the first electrode terminals when viewed from a thickness direction which is perpendicular to the element front surface.

Bonding structure
20250006684 · 2025-01-02 ·

According to an example aspect of the present invention, there is provided a bonding structure for forming at least one electrical connection between an optoelectronic component and a photonic substrate. The bonding structure comprises a pillar structure between the optoelectronic component and the photonic substrate, and a bonding layer comprising bonding material on the pillar structure. The pillar structure for at least one individual electrical connection comprises at least two portions and at least one gap between the portions for receiving extra bonding material of the bonding layer.

Chip structure, semiconductor package, and fabricating method thereof
12506101 · 2025-12-23 · ·

A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.