A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.

A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

A light-emitting module includes a common carrier; a plurality of semiconductor devices formed on the common carrier, and each of the plurality of semiconductor devices including three semiconductor dies; a carrier including a connecting surface; a third bonding pad and a fourth bonding pad formed on the connecting surface; and a connecting layer. One of the three semiconductor dies includes a stacking structure; a first bonding pad; and a second bonding pad with a shortest distance less than 150 microns between the first bonding pad. The connecting layer includes a first conductive part including a first conductive material having a first shape; and a blocking part covering the first conductive part and including a second conductive material having a second shape with a diameter in a cross-sectional view. The first shape has a height greater than the diameter.

Disclosed is a display device and a method of manufacturing the same, wherein an end portion of a pad provided on a first substrate is spaced apart and separated from an upper surface of the first substrate, and a connection electrode electrically connected with the pad is in contact with a lateral surface of the pad and a lower surface of the pad.

Provided is a printed wiring board comprising: a substrate; a conductive layer including a land and a wiring and formed on a surface of the substrate, the wiring having a width smaller than the land and drawn from the land; and an insulating layer formed on the conductive layer. The insulating layer has an opening corresponding to a position of the land, and an edge of the opening runs above the land and above one of edges in a width direction of the wiring.

A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.

A semiconductor device includes a first semiconductor element, a first connection terminal formed on a lower surface of the first semiconductor element, a second semiconductor element mounted on the lower surface of the first semiconductor element so that the second semiconductor element partially overlaps the first semiconductor element in plan view, a second connection terminal formed on a lower surface of the second semiconductor element, and a wiring substrate on which the first and second semiconductor elements are mounted. The wiring substrate includes first and second connection pads electrically connected to the first connection terminal and the second connection terminal, respectively. The semiconductor device further includes a third connection terminal formed on the first connection pad and electrically connected to the first connection terminal. One of the first connection terminal and the third connection terminal is a metal post, and the other is a solder ball.

A photodetector-array and fabrication method thereof are disclosed. The photodetector-array includes a first and second semiconductor structures having respective active regions defining respective pluralities of active photodetectors and active readout integrated circuit pixels (RICPs) electronically connectable to one another respectively. The first and second semiconductor structures are made with different semiconductor materials/compositions having different first and second coefficients of thermal expansion (CTEs) respectively. The pitch distances of the active photodetectors and the pitch distances of the respective active RICPs are configured in accordance with the difference between the first and second CTEs, such that at high temperatures, at which electrical coupling between the first and second semiconductor structures is performed, the electric contacts of the active photodetectors and of their respective RICPs overlap. Accordingly, after the first and second semiconductor structures are bonded together, at least 99.5% of the active photodetector are electrically connected with their respective RICPs.

A method is provided. The method includes attaching a bridge layer to a first substrate. The method also includes forming a first connector, the first connector electrically connecting the bridge layer to the first substrate. The method also includes coupling a first die to the bridge layer and the first substrate, and coupling a second die to the bridge layer.

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.