In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.

A semiconductor device has a plurality of interconnected modular units to form a 3D semiconductor package. Each modular unit is implemented as a vertical component or a horizontal component. The modular units are interconnected through a vertical conduction path and lateral conduction path within the vertical component or horizontal component. The vertical component and horizontal component each have an interconnect interposer or semiconductor die. A first conductive via is formed vertically through the interconnect interposer. A second conductive via is formed laterally through the interconnect interposer. The interconnect interposer can be programmable. A plurality of protrusions and recesses are formed on the vertical component or horizontal component, and a plurality of recesses on the vertical component or horizontal component. The protrusions are inserted into the recesses to interlock the vertical component and horizontal component. The 3D semiconductor package can be formed with multiple tiers of vertical components and horizontal components.

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Integrated circuit package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce a die to a substrate clearance and related fabrication methods are disclosed. The IC package includes die interconnects coupled to first metal pad(s) of respective metal interconnects of a metallization layer of the substrate to provide support and signal routing paths. To reduce clearance between the die and the substrate and consequently the height of the IC package, a second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is coupled to the first metal pad(s). Solder is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate. When the solder is heated to form the solder joint, the solder flows along the reduced cross-sectional area of the second, additional metal pad(s).

Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a substrate and a metallization stack having an interface that is parallel to the first and second surfaces, the substrate including voltage converter (VC) circuitry and compute circuitry; and a second IC die having a fourth surface, wherein the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die by an interconnect.

One or more electrical interconnects are formed beneath a device region within a volume of semiconductor material in which electronic devices are formed. The buried interconnects extended in a lateral direction parallel to surfaces of the die toward an edge of the semiconductor die. Such buried interconnects can be exposed at edges of the die to provide electrical contacts along those edges and can be coupled to electronic devices formed within the device region as alternatives to or in addition to contacts formed on top or bottom surfaces of the die.

An electronic device can include a first die, a second die, and an interconnect. The first die or the second die has a principal function as a power module or a memory. The first die includes a first bond pad, and the second die includes a second bond pad. The device sides of the first and second dies are along the same sides as the first and second bond pads. In an embodiment, the first die and the second die are in a chip first, die face-up configuration. The first and the second bond pads are electrically connected along a first solderless connection that includes the interconnect. In another embodiment, each material within the electrical connection between the first and the second bond pads has a flow point or melting point temperature of at least 300 C.

A semiconductor package includes a first substrate including a first wiring layer inside the first substrate, a second substrate including a second wiring layer inside the second substrate, and a mold layer between the first substrate and the second substrate. An upper surface of the mold layer is on a same plane as upper surfaces of the first substrate and the second substrate. The package includes a first connecting film on each of the upper surface of the first substrate and the upper surface of the second substrate, the first connecting film connecting the first substrate and the second substrate, and a first semiconductor chip on the upper surface of the first substrate. The first semiconductor chip is spaced apart from the first connecting film, and an upper surface of the first connecting film is lower than an upper surface of the first semiconductor chip.