The present application discloses an underfill for chip packaging, including 19-25% of epoxy resin, 55-60% of filler, 15-25% of curing agent and 0.5-0.8% of accelerator in mass percentage, wherein the curing agent includes a polycondensate of paraxylene and dihydroxynaphthalene and a polycondensate of paraxylene and naphthol. Both of the polycondensate of paraxylene and dihydroxynaphthalene and the polycondensate of paraxylene and naphthol are selected to be used in the underfill for chip packaging in the present application, so that the underfill has stronger adhesiveness after being cured. In addition, the present application further provides a chip packaging structure using the underfill.

The disclosure describes a lidded flip chip package allowing for a thermal interface material (TIM) with fluidity, like a liquid metal, including: a lid, a sealing ring for forming a sealed gap between a flip chip and the lid, a storage tunnel as a reservoir for accepting or releasing a liquid metal from or to the sealed gap, and an injection tunnel for filling a liquid metal into the sealed gap, wherein a self-sealing plug structure is integrated with the storage tunnel and the injection tunnel, the sealed gap is completely filled with a liquid metal, and a portion of the storage tunnel is filled with the same liquid metal and its remaining portion is filled with a gas. The disclosure also describes a method for filling a liquid metal into the lidded flip chip package based on the self-sealing plug structure.

Aspects of the present technology are directed toward three-dimensional (3D) stacked processing systems characterized by high memory capacity, high memory bandwidth, low power consumption and small form factor. The 3D stacked processing systems include a plurality of processor chiplets and input/output circuits directly coupled to each of the plurality of processor chiplets.

Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and covering a cover plate wafer on the first surface of the substrate wafer to seal up the groove so as to form a semiconductor package structure, a gap between the substrate wafer, the semiconductor die stack and the cover plate wafer being not filled with a filler.

An Integrated Circuit (IC) package has a ferrite-dielectric shield between a planar inductor coil and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in the inductor coil from reaching the semiconductor chip. The shield has a ferrite layer surrounded by upper and lower dielectric laminate layers to prevent electrical shorts. The center end of the inductor coil connects to the semiconductor chip through a center post that fits through an opening in the shield that is over the air core center of the inductor coil. The center post can connect to a die attach pad that the semiconductor chip is mounted to. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors. The outer end of the inductor coil connects to lead-frame outer risers also having external package connectors such as pins or bonding balls.

An Integrated Circuit (IC) package has a ferrite-dielectric shield between planar transformer coils and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in transformer coils from reaching the semiconductor chip. Multiple layers of planar transformer coils serve as primary or secondary coils and can be connected together in series or parallel using center posts and coil extensions from outer coil windings to lead-frame risers that also have external package connectors such as pins or bonding balls. The center winding of an upper transformer coil connects to the semiconductor chip on a die attach pad through a center post that fits through an opening in the shield that is over the air core center of the transformer coil. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors.

A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.

The present application discloses an underfill for chip packaging, including 19-25% of epoxy resin, 55-60% of filler, 15-25% of curing agent and 0.5-0.8% of accelerator in mass percentage, wherein the curing agent includes a polycondensate of paraxylene and dihydroxynaphthalene and a polycondensate of paraxylene and naphthol. Both of the polycondensate of paraxylene and dihydroxynaphthalene and the polycondensate of paraxylene and naphthol are selected to be used in the underfill for chip packaging in the present application, so that the underfill has stronger adhesiveness after being cured. In addition, the present application further provides a chip packaging structure using the underfill.

A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

Methods, systems, and devices related to a memory die and a logic die having a wafer-on-wafer bond therebetween. A memory die can include a memory array and a plurality of input/output (IO) lines coupled thereto. A logic die can include to a deep learning accelerator (DLA). The memory die can be coupled to the logic die by a wafer-on-wafer bond. The wafer-on-wafer bond can couple the plurality of IO lines to the DLA.