A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.

A display device includes a base layer including a first portion and a second portion disposed around the second portion; a display unit disposed on a first surface of the first portion and including a light emitting element; a driving circuit disposed on a first surface of the second portion and including a driving chip; a support member attached to a second surface of the first portion and a second surface of the second portion; and an adhesive member disposed between the base layer and the support member, wherein the adhesive member includes a first adhesive member having a first elastic modulus and a second adhesive member having a second elastic modulus that is higher than the first elastic modulus, and the second adhesive member overlaps the driving circuit.

A display device includes a base layer including a first portion and a second portion disposed around the second portion; a display unit disposed on a first surface of the first portion and including a light emitting element; a driving circuit disposed on a first surface of the second portion and including a driving chip; a support member attached to a second surface of the first portion and a second surface of the second portion; and an adhesive member disposed between the base layer and the support member, wherein the adhesive member includes a first adhesive member having a first elastic modulus and a second adhesive member having a second elastic modulus that is higher than the first elastic modulus, and the second adhesive member overlaps the driving circuit.

Methods and apparatus to embed host dies in a substrate are disclosed An apparatus includes a first die having a first side and a second side opposite the first side. The first side includes a first contact to be electrically coupled with a second die. The second side includes a second contact. The apparatus further includes a substrate including a metal layer and a dielectric material on the metal layer. The first die is encapsulated within the dielectric material. The second contact of the first die is bonded to the metal layer independent of an adhesive.

The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.

The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.

A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.

A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Disclosed is a semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, a connection solder pattern between the package substrate and the semiconductor chip, and a dummy bump between the package substrate and the semiconductor chip and spaced apart from the connection solder pattern. The connection solder pattern includes a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer. The dummy bump includes a dummy pillar and a dummy solder pattern. A thickness of the dummy solder pattern is less than a thickness of the connection solder pattern. A melting point of the dummy solder pattern is greater than that of the connection solder layer.