The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

A semiconductor package including a molded power delivery module arranged between a package substrate and a semiconductor chip and including a plurality of input conductive structures and a plurality of reference conductive structures, wherein the input conductive structures alternate between the plurality of reference conductive structures, wherein the input conductive structure is electrically coupled with a chip input voltage terminal and a package input voltage terminal, wherein each of the plurality of reference conductive structures are electrically coupled with a semiconductor chip reference terminal and a package reference terminal.

A semiconductor package includes: a substrate; a semiconductor chip disposed on a first surface of the substrate; solder bumps disposed between a first surface of the semiconductor chip and the substrate; and a redistribution layer provided on a second surface, opposite to the first surface, of the semiconductor chip. The substrate includes substrate patterns, and the substrate patterns cover a second surface of the substrate. The substrate patterns cover 60% to 100% of a total area of the second surface of the substrate.

A semiconductor package includes: a substrate; a semiconductor chip disposed on a first surface of the substrate; solder bumps disposed between a first surface of the semiconductor chip and the substrate; and a redistribution layer provided on a second surface, opposite to the first surface, of the semiconductor chip. The substrate includes substrate patterns, and the substrate patterns cover a second surface of the substrate. The substrate patterns cover 60% to 100% of a total area of the second surface of the substrate.

A semiconductor chip may include: a body portion including a front surface and a back surface; penetrating electrodes penetrating the body portion; and back connection electrodes disposed over the back surface of the body portion and connected to the penetrating electrodes, wherein the penetrating electrodes include a power penetrating electrode for transmitting a power voltage and a ground penetrating electrode for transmitting a ground voltage, the back connection electrodes include a power back connection electrode connected to the power penetrating electrode and a ground back connection electrode connected to the ground penetrating electrode, and one power back connection electrode is connected with two or more power penetrating electrodes, and one ground back connection electrode is connected with two or more ground penetrating electrodes.

An integrated circuit (IC) package comprising a first die, including an active layer opposite a backside surface of the first die supporting a plurality of backside pads is provided. The IC package also incorporates a package substrate coupled to the active layer. The package pads on the package substrate correspond to the plurality of backside pads. A passive device comprising a plurality of wire bonds is coupled to the plurality of backside pads and the plurality of package pads. The passive device may also comprise a plurality of wire bonds coupled to the package pads by through silicon vias (TSVs). Multiple dies may be coupled with die-to-die wire bonds coupled to backside pads on each die.

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.