A package includes a first redistribution structure, a bridge structure, an adhesive layer, a plurality of conductive pillars, an encapsulant, a first die, and a second die. The bridge structure is disposed on the first redistribution structure. The adhesive layer is disposed between the bridge structure and the first redistribution structure. The conductive pillars surround the bridge structure. A height of the conductive pillars is substantially equal to a sum of a height of the adhesive layer and a height of the bridge structure. The encapsulant encapsulates the bridge structure, the adhesive layer, and the conductive pillars. The first die and the second die are disposed over the bridge structure. The first die is electrically connected to the second die through the bridge structure. The first die and the second die are electrically connected to the first redistribution structure through the conductive pillars.

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Reliability of joining between semiconductor chips is improved by promoting filling of a sealing resin into a gap formed between the semiconductor chips.

A semiconductor device includes: a first semiconductor chip, which has a plurality of first electrodes on a surface; a second semiconductor chip, which is disposed to be separated by a gap from the surface of the first semiconductor chip, and which includes an inner peripheral area that has a plurality of second electrodes connected to each of the first electrodes on a surface and an outer peripheral area that surrounds the inner peripheral area and has a thickness thinner than the thickness of the inner peripheral area; and a sealing resin, which is respectively filled between the surface of the first semiconductor chip and the inner peripheral area, and between the surface of the first semiconductor chip and the outer peripheral area.

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semi-conductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

In examples, a semiconductor package comprises a semiconductor die having a device side comprising circuitry formed therein; a passivation layer abutting the device side; first and second horizontal metal members coupled to the device side by way of vias extending through the passivation layer, the first and second horizontal metal members having thicknesses ranging from 4 microns to 25 microns; first and second metal posts coupled to and vertically aligned with the first and second metal members, respectively, the first and second metal posts having vertical thicknesses ranging from 10 microns to 80 microns; first and second solder bumps coupled to the first and second metal posts, respectively; and a ball grid array (BGA) substrate coupled to the first and second solder bumps. The BGA substrate comprises a substrate member; first and second horizontal top metal members abutting the substrate and coupled to the first and second solder bumps, respectively; first and second vias coupled to the first and second horizontal top metal members and extending through the substrate member; and first and second horizontal bottom metal members abutting the substrate and coupled to the first and second vias, respectively. The first horizontal top metal member, the first via, and the first horizontal bottom metal member are electrically coupled to a signal terminal of the semiconductor die and are configured to provide signal currents. The second horizontal top metal member, the second via, and the second horizontal bottom metal member are electrically coupled to a power terminal of the semiconductor die and are configured to provide power currents.