A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected to the power support structure, and (ii) a second cache region, which overlies and is electrically connected to the first cache region.

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.

An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.

An electronic device includes: a first substrate having a first surface and a second surface opposite from the first surface; a second substrate facing the first surface; driven elements provided at the second substrate; a drive circuit facing the second surface; a first interconnect provided at the first surface; a second interconnect provided at the second surface; a through-substrate interconnection part penetrating the first substrate in a thickness direction thereof; a first bump part; and a second bump part. The drive circuit is capable of outputting drive signals for driving the driven elements. The through-substrate interconnection part electrically connects the first interconnect and the second interconnect. The first bump part electrically connects the first interconnect and the driven elements. The second bump part electrically connects the second interconnect and the drive circuit. The through-substrate interconnection part has an electrical resistance lower than an electrical resistance of the second bump part.